Redundant Latch Circuit for Soft Error Self-Correction
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Solution Overview
Problem
The increasing probability of soft errors in electronic circuitry due to shrinking device sizes and reduced supply voltages poses a significant threat to data integrity, as errors in critical calculations can be unacceptable.
Innovation Solution
A latch circuit with redundancy in data and clock paths is employed, using redundant clock signals and data lines that carry the same logical signal, allowing the circuit to maintain correct data even if a soft error occurs on either line, through a network of transistors and inverters that counteract errors by maintaining internal node states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device sizes are shrunk and supply voltages are reduced, then integration density and power efficiency are improved, but the probability of soft errors increases
Solution Approach 1:
The latch circuit is divided into two symmetric halves, each with its own data path (d1/d2) and clock path (clk1/clk2). This segmentation creates redundant independent paths that can tolerate errors in one path without affecting the other, directly addressing the soft error probability issue while maintaining integration density through compact layout.
Solution Approach 2:
Redundant circuit elements are built into the latch structure before operation begins. The symmetric design with duplicate data and clock paths provides pre-established protection against soft errors, allowing the circuit to withstand errors without requiring external correction mechanisms.
2Reliability
If redundant data paths and clock paths are used, then soft error protection is improved, but circuit complexity increases
Solution Approach 1:
While the overall structure is symmetric for redundancy, the internal transistor arrangements within each half utilize asymmetric sizing and configuration to optimize performance. This allows the redundant structure to provide error protection while minimizing the complexity increase through optimized component design within each symmetric unit.
Solution Approach 2:
The two symmetric halves of the latch share common output nodes and control logic, merging certain functions to reduce overall complexity. The redundant paths are combined at the output stage, allowing error protection without proportionally increasing the total component count and circuit complexity.
Data Source
AI summary
An apparatus is described having a latch circuit. The latch circuit includes redundant data inputs, redundant data outputs, redundant clock inputs and circuitry to self-correct a soft-error.