Redundant Memory Array Design for Efuse Yield Improvement
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Solution Overview
Problem
Existing efuse memory technology faces low manufacturing yield due to programming failures and reading errors, which often require large redundancy areas and result in inefficient memory cell replacement.
Innovation Solution
A memory array design with redundant memory cells in each row and column, where each redundant cell stores the same data as the corresponding memory cell, allowing for programming and reading through a specific path formed by MOS transistors and sense amplifiers, enabling data correction and improved yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large redundancy areas are used to compensate for programming failures and reading errors, then manufacturing yield is improved, but device area and complexity increase
Solution Approach 1:
The patent merges the functionality of separate redundancy rows and columns into a unified redundant array structure. The redundant memory cells are integrated into the existing array architecture, sharing common bitlines and wordlines with functional memory cells. This consolidation reduces the overall redundancy area compared to traditional approaches that require dedicated redundancy blocks.
Solution Approach 2:
The redundant memory cells serve multiple functions: they can replace failed functional memory cells, provide backup storage capacity, and maintain array structural integrity. The same redundant cells can be used for different replacement purposes depending on where failures occur, eliminating the need for separate redundancy structures for different failure modes.
2Reliability
If traditional redundancy structures are used to handle programming failures, then reliability is improved, but memory cell replacement efficiency decreases
Solution Approach 1:
The patent segments the redundancy management into modular units where individual redundant cells can be independently activated to replace failed cells. This segmentation allows for targeted replacement of only the failed memory cells rather than requiring systematic replacement of entire rows or columns, significantly improving replacement efficiency.
Solution Approach 2:
The redundant memory cells are pre-configured and positioned within the array structure before failures occur. The redundancy mapping and replacement pathways are established in advance, allowing for rapid response to programming failures without requiring complex real-time analysis or extensive reconfiguration operations.
3Ease of manufacture
If efuse melting is used to store data, then manufacturing process simplicity is maintained, but programming precision and reliability decrease
Solution Approach 1:
The patent implements feedback mechanisms through sense amplifiers that read the resistance state of efuse elements after programming attempts. This feedback allows for verification of successful programming and detection of programming failures, enabling corrective actions such as re-programming or activation of redundant cells, thereby improving overall programming precision without complicating the manufacturing process.
Solution Approach 2:
The redundant memory cells are prepared in advance with identical structural and electrical characteristics to functional cells. This preliminary preparation ensures that when replacement is needed, the substitution can be performed with high precision using the same manufacturing processes, maintaining ease of manufacture while improving reliability through the availability of pre-validated backup cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the manufacturing yield of memory devices by allowing accurate data reading and programming even after failures, reducing the need for extensive redundancy areas and improving overall device performance.
Implementation Method 1
The initial resistance of an efuse is considerably small, but when a high current flows through the efuse, the efuse may be melted and the resistance multiplies
Data Source
AI summary
The present invention provides a memory. The memory includes a plurality of memory cells arranged as an array with a plurality of rows and a plurality of column. A memory cell is connected to at least one redundant memory cell in a same row for storing same data as the memory cell; and a column of memory cells correspond to one redundant column of redundant memory cells wherein each redundant memory cell in the redundant column stores same data as the memory cell in a same row.