Redundant Memory Array Section Replacement Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory systems face issues with block failures of three adjacent memory sections due to limited redundant memory, leading to entire memory device inoperability, as existing architectures are not efficient in replacing defective memory sections across different banks.
Innovation Solution
Implementing a redundant memory architecture with shorter digit lines in redundant memory arrays, allowing for sharing of sense-amplifiers and using dummy digit lines for noise immunity, enabling the replacement of entire memory sections and reducing the overall size of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If limited redundant memory is provided for each memory section, then the area occupied by redundant memory is reduced, but the ability to repair defective memory sections is insufficient
Solution Approach 1:
The redundant memory array is designed to serve multiple memory sections simultaneously. Instead of dedicating limited redundant memory to each individual memory section, a shared redundant memory array can replace defective sections from multiple banks, maximizing the utility of redundant memory resources.
Solution Approach 2:
The patent introduces a new dimensional approach by creating a separate redundant memory array that operates independently from the main memory array structure. This allows redundant memory to be organized and allocated differently, enabling more flexible repair strategies across multiple memory sections without being constrained by traditional per-section allocation.
2Ease of repair
If redundant memory is allocated per memory section, then local repair capability is improved, but unused redundant memory cannot assist other memory sections
Solution Approach 1:
The redundant memory array is designed as a universal resource that can be allocated to repair any defective memory section within the memory device. The system maintains local repair capability while enabling cross-sectional assistance through a shared pool of redundant memory that can be dynamically assigned based on failure patterns.
Solution Approach 2:
The patent implements dynamic allocation of redundant memory resources. Instead of static per-section allocation, the system can adaptively assign redundant memory sections to different main memory sections based on real-time needs, allowing unused redundant memory in one area to assist other areas experiencing failures.
3Device complexity
If open-digit line sense amplifier architecture is used, then memory section organization is simplified, but block failures of three adjacent memory sections can occur
Solution Approach 1:
The patent addresses block failure susceptibility by introducing redundant memory sections that can replace failed sections within blocks. The segmentation principle is applied by dividing the memory into manageable units with dedicated redundant replacements, allowing localized repair of block failures without affecting the entire memory device.
Solution Approach 2:
The system implements prior cushioning by pre-allocating redundant memory sections before failures occur. These redundant sections serve as a buffer or cushion against block failures, allowing the system to withstand and recover from failures of three adjacent memory sections without catastrophic loss of functionality.
Data Source
AI summary
Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.