Redundant Memory Controller Failover for System Continuity
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Solution Overview
Problem
Conventional processor-to-memory architectures lack a mechanism for redundant memory access, leading to data loss in case of processor failure or power outages, as each processor relies on a single access point to dedicated or shared memory.
Innovation Solution
Implementing a redundant memory access system with multiple controllers connected to the same bank of memory, where a primary controller uses the memory for storage and a secondary redundant controller takes over in case of failure, ensuring continuous operation by accessing the common memory and supporting redundant data/address/control interconnect paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single memory controller is used for each processor, then the system structure is simple and easy to implement, but the system reliability deteriorates because data loss occurs upon processor or controller failure
Solution Approach 1:
The system segments the memory controller function into multiple independent controllers (primary and redundant) that can independently access the same memory bank. This segmentation allows the system to divide the single point of failure into multiple redundant paths, where each controller can take over if another fails.
Solution Approach 2:
The system changes the operational state of the redundant controller from inactive to active based on failure detection. When the primary controller fails, the redundant controller transitions from a standby state to an active state, changing the system's operational parameters to maintain reliability without permanently increasing complexity.
2Reliability
If multiple controllers are connected to the same memory bank, then system reliability improves through failover capability, but device complexity increases due to additional controllers and control logic
Solution Approach 1:
The redundant controller is pre-configured and initialized in advance, with all necessary control logic and memory mappings prepared before failure occurs. This preliminary setup allows the redundant controller to take over immediately upon failure detection, reducing the complexity of real-time failover management while maintaining high reliability.
Solution Approach 2:
The patent introduces control logic as an intermediary that manages the interaction between the primary and redundant controllers. This intermediary handles the complexity of controller coordination, failure detection, and state transitions, allowing the controllers themselves to remain relatively simple while achieving sophisticated failover behavior.
3Productivity
If the redundant controller remains inactive during normal operation, then system resources are optimized and the redundant controller can contribute to workload, but the system loses time during failover as initialization is required
Solution Approach 1:
The redundant controller performs preliminary initialization and maintains a ready state during normal operation, keeping essential data structures and control logic prepared in advance. This allows the controller to transition to active operation with minimal delay when failover is required, balancing resource utilization with fast response time.
Data Source
AI summary
A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory, and a design structure on which the subject circuit resides is provided. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.