Redundant Memory Validation via Dual Ports
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Solution Overview
Problem
Safety-critical systems face corruption of stored values due to ionizing radiation and background contamination, leading to 'soft errors' that existing technologies fail to mitigate effectively.
Innovation Solution
A method and system for redundantly validating values stored in memory using dual ports with coherent access, where an instruction processor and a check circuit verify expected values against calculated check values, and perform recovery operations when mismatches are detected, ensuring high reliability through multiple independent checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache error detection and correction are absent to reduce device complexity, then reliability is compromised due to soft errors from radiation and contamination
Solution Approach 1:
The patent divides the validation function into two independent segments: an instruction processor that validates values read via a first port, and a check circuit that validates values read via a second port. This segmentation allows each component to perform validation independently without requiring complex error detection and correction circuitry in the cache, thereby maintaining reliability while avoiding increased device complexity
Solution Approach 2:
The patent introduces an intermediary validation mechanism where the instruction processor and check circuit act as mediators between the memory arrangement and the processing logic. These intermediaries perform validation of values before they are used, preventing soft errors from propagating without requiring complex error correction in the cache itself
2Reliability
If dual ports with coherent access are used to enable redundant validation, then device complexity increases, but reliability improves through multiple independent checks
Solution Approach 1:
The patent merges the validation function into the existing dual-port memory architecture, where both the instruction processor and check circuit validate values from the same memory arrangement through different ports. This merging allows redundant validation to be performed using existing infrastructure, improving reliability without proportionally increasing device complexity
Solution Approach 2:
The dual ports of the memory arrangement serve multiple functions: they enable both normal data access and redundant validation operations. The instruction processor uses one port for validation while the check circuit uses the other, allowing the same memory infrastructure to support both performance and reliability requirements without requiring separate validation memory structures
Data Source
AI summary
Methods and systems redundantly validate values that are stored in a memory arrangement. The memory arrangement includes a first port and a second port that provide coherent access to one or more caches in the memory arrangement, and the first and second ports provide this coherent access at the same priority level. An instruction processor verifies that a first expected value matches a first check value calculated from the values as read from the memory arrangement via the first port. A check circuit verifies that a second expected value matches a second check value calculated from the values as read from the memory arrangement via the second port. A recovery operation is performed in response to the first or second expected values not matching the first and second check values, respectively.