Redundant PLL Clock Switching for Harsh-Environment Reliability
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Solution Overview
Problem
Existing PLL circuits in harsh environments, such as space, can experience extended periods without output clock signals due to temporary or permanent disruptions from charged particles, leading to unreliable synchronized output clock signals.
Innovation Solution
A system of phase-locked loop circuits with multiplexing capabilities using lock signals from each PLL ensures a seamless transition to maintain a glitch-free output clock signal by selecting a locked PLL, utilizing majority voter circuits and multiplexer logic to synchronize and align output clocks with input reference clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single PLL circuit is used in a harsh environment, then the device complexity is reduced, but the reliability of the output clock signal deteriorates due to temporary or permanent disruptions from charged particles
Solution Approach 1:
The system divides the single PLL function into multiple independent PLL circuits (at least two PLLs). Each PLL circuit operates independently and can be selectively activated based on its lock status, ensuring that if one PLL fails due to charged particle disruption, another can take over to maintain reliable output clock signal generation.
Solution Approach 2:
The system dynamically changes the operational parameters by monitoring the lock status of each PLL circuit and switching between them based on their current state. This parameter-based selection ensures that only PLLs in a locked state contribute to the output, maintaining signal reliability while adapting to changing environmental conditions.
2Reliability
If multiple PLL circuits are used with multiplexing, then the reliability of the output clock signal is improved, but the device complexity increases due to additional multiplexer circuits and lock signal processing
Solution Approach 1:
Each PLL circuit provides a lock status signal that serves as feedback to the multiplexer control logic. This feedback mechanism enables the system to automatically detect when a PLL loses lock due to environmental factors and switch to an alternative PLL, maintaining output reliability without requiring complex manual intervention or overly sophisticated control circuits.
Solution Approach 2:
The multiplexer acts as an intermediary component that selectively routes the output clock signal from one of multiple PLL circuits based on their lock status. This intermediary element simplifies the overall system architecture by providing a straightforward switching mechanism that manages the complexity of multiple PLLs without requiring elaborate control logic.
3Adaptability or versatility
If PLL circuits operate in harsh environments, then the adaptability to space or rugged applications is improved, but the stability of the output clock signal deteriorates due to charged particle disruptions
Solution Approach 1:
The system continuously monitors the lock status of each PLL circuit in advance before failures occur. By detecting lock loss conditions early and having pre-configured alternative PLL circuits ready, the system can switch to a stable output source before disruptions affect the overall signal stability, ensuring continuous reliable operation in harsh environments.
Solution Approach 2:
The system prepares backup PLL circuits in advance that can immediately take over if the primary PLL fails due to charged particle disruptions. This cushioning approach ensures that there is no gap in stable output clock signal generation, as the backup PLLs are already configured and ready to provide stable operation when needed.
Data Source
AI summary
A phase-locked loop (PLL) circuit system includes first, second, and third PLL circuits, first, second, and third multiplexer circuits coupled to the first, second, and third PLL circuits, and a majority voter circuit coupled to the first, second, and third PLL circuits, wherein the PLL circuit system provides a glitch-free output clock signal by selecting a locked PLL circuit. Each PLL circuit includes a first input for receiving a reference clock signal; a second input for receiving a feedback clock signal; a first output for providing an output clock signal; a second output for providing a lock signal; and a return path coupled between the first output and the second input. The return path can be a direct connection or a logic circuit. Each multiplexer circuit includes three lock inputs, a first clock input, a second clock input, a defeat input, and a clock output.