Redundant Processing Elements Error Detection Lockstep
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Solution Overview
Problem
In data processing systems requiring functional safety, existing redundancy mechanisms face challenges in managing correctable errors without incurring significant latency or performance impact, particularly in maintaining lockstep between processing elements to detect divergence effectively.
Innovation Solution
The system employs error detection and correction circuitry within each processing element to signal correctable errors to other elements, allowing them to delay processing and maintain a predetermined time offset, thereby ensuring reliable divergence detection without incurring error correction latency on all operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction circuitry corrects correctable errors in processing elements, then system reliability is improved, but processing latency increases and performance deteriorates
Solution Approach 1:
The patent extracts the error correction latency from the critical processing path by having erroneous processing elements signal correctable errors to non-erroneous elements. This allows non-erroneous elements to delay their processing independently of actual error correction operations, separating the timing synchronization function from the error correction function.
Solution Approach 2:
Non-erroneous processing elements perform preliminary delay actions based on signals from erroneous elements before divergence detection occurs. This preliminary timing adjustment prevents future divergence without waiting for actual error correction to complete, maintaining synchronization proactively rather than reactively.
2Measurement precision
If processing elements operate in lockstep with strict timing synchronization, then divergence detection accuracy is improved, but processing flexibility and adaptability deteriorate
Solution Approach 1:
The patent introduces dynamic timing adjustments where processing elements can flexibly delay their operations based on real-time error signals from other elements. This dynamic synchronization maintains lockstep operation when needed while allowing adaptive timing adjustments when errors occur, combining rigid synchronization with flexible error handling.
Solution Approach 2:
Erroneous processing elements provide feedback signals to non-erroneous elements about correctable errors. This feedback mechanism allows the system to maintain synchronization by adjusting timing based on actual error conditions, preserving divergence detection accuracy while adapting to error states.
3Reliability
If all processing elements perform error correction operations, then system resilience to errors is improved, but overall processing throughput and productivity deteriorate
Solution Approach 1:
Instead of all processing elements performing error correction operations, only non-erroneous elements perform delay operations based on signals from erroneous elements. This partial action approach provides sufficient error handling resilience without requiring every element to execute full error correction sequences, preserving processing throughput.
Solution Approach 2:
Non-erroneous processing elements serve multiple functions: they perform their primary processing task and simultaneously act as timing reference elements for the entire system. By using these elements' delay capability as a universal synchronization mechanism, the system achieves error resilience without requiring dedicated error correction infrastructure in every element.
Data Source
AI summary
An apparatus has two or more processing elements to redundantly process a same processing workload; and divergence detection circuitry to detect divergence between the plurality of processing elements. When a correctable error is detected by error detection circuitry of an erroneous processing element, the erroneous processing element signals detection of the correctable error to another processing element, to control the other processing element to delay processing to maintain a predetermined time offset between the erroneous processing element and the other processing element.