Redundant Processor Clocking for Synchronized Error Detection
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Solution Overview
Problem
In parallel-redundant processing units, ensuring identical logical switch states between safety controllers for accurate cross comparison and error detection is challenging due to potential synchronization issues and deviations in clock frequencies.
Innovation Solution
A circuit comprising two processing units with functionally identical logic circuits and memory storing identical control programs, synchronized by a third clock source, which queries and outputs input states after a predefined nominal duration, and compares control signals to detect deviations, generating an error signal if discrepancies are found.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parallel-redundant processing units use a common synchronization signal to trigger processing cycles, then processing can be coordinated between units, but clock frequency deviations cause synchronization errors and processing deviations
Solution Approach 1:
The patent divides the single synchronization function into two separate synchronization signals: a first synchronization signal for the first processing unit and a second synchronization signal for the second processing unit. Each signal is generated independently based on its respective clock source, eliminating the propagation of clock frequency deviations between units while maintaining coordinated processing cycles
Solution Approach 2:
The mode selector switch serves as an intermediary component that both processing units query to ensure they operate on identical logical switch states. This intermediary ensures that even with independent clock sources, both units make identical decisions about program execution, preventing processing deviations
2Ease of operation
If a mode selector switch state is read before each processing cycle to control execution, then program execution can be controlled, but clock frequency deviations may cause different units to read the state at different times leading to inconsistent decisions
Solution Approach 1:
Both processing units are designed to query the mode selector switch state at the beginning of each processing cycle before executing any program instructions. This preliminary action ensures that both units base their execution decisions on the same logical switch state, maintaining decision consistency even with independent clock sources
Solution Approach 2:
The system incorporates cross-comparison of processing results between the two redundant units. This feedback mechanism detects any processing deviations that may have occurred despite the synchronization measures, providing an additional layer of reliability verification
3Measurement precision
If processing cycles are executed synchronously based on identical clock timing, then cross comparison of results is simplified, but any clock frequency deviation prevents accurate cross comparison and error detection
Solution Approach 1:
The patent segments the clocking system into independent clock sources for each processing unit, eliminating the propagation of frequency deviations. Each unit executes processing cycles independently but can still perform cross-comparison of results, maintaining error detection capability without requiring identical clock timing
Solution Approach 2:
The cross-comparison mechanism serves as a feedback system that compares processing results from both redundant units. Any deviations detected through this comparison trigger error detection, maintaining reliability even with independent clock sources by verifying result consistency
Data Source
AI summary
A circuit is provided that has three clock sources, a first processing unit connected to the first clock source, a second processing unit connected to the second clock source, and an input unit. The first processing unit has a first logic circuit and a first memory circuit connected to the first logic circuit, wherein a first set of instructions, which is designed to implement a first control program when executed by the first logic circuit, is stored in the first memory circuit, wherein the first clock source specifies a clock timing of the execution of the first set of instructions. The second processing unit has a second logic circuit and a second memory circuit connected to the second logic circuit, wherein a second set of instructions, which is designed to implement a second control program when executed by the second logic circuit, is stored in the second memory circuit.