Redundant Processor Synchronization via State History

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As integrated circuit complexity and operating voltages decrease, soft errors due to particle strikes increase, making effective error mitigation in data processing systems challenging, particularly when redundant processors operate out of sync, leading to potential false error detections.

Innovation Solution

The synchronization of redundant processors using state history, where each processor's state is stored and compared as a digital signature, allowing for synchronization at the most recent matching instruction boundary, thereby preventing false error invocations and ensuring coordinated handling of inputs and interrupts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If redundant processors operate out of sync to improve productivity, then instruction execution speed increases, but false error detections occur due to non-synchronized input delivery

Engineering Contradiction:
Improveinstruction execution speedVSAvoiderror detection accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by checking processor synchronization status before delivering inputs or interrupts. The error handler determines whether processors are synchronized at instruction boundaries prior to input delivery, and only delivers inputs when synchronization is confirmed. This prevents false error detections while allowing processors to operate out of sync during execution, thus maintaining both productivity and reliability.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If redundant processors operate in lockstep to ensure synchronization, then false error detections are prevented, but instruction execution speed decreases

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidinstruction execution speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies dynamics by allowing processors to dynamically switch between synchronized and asynchronous operation modes. During normal execution, processors can operate independently at different speeds (asynchronous). When input delivery is required, the system dynamically checks synchronization status and temporarily coordinates processors to be synchronized. This dynamic approach maintains high execution speed while ensuring synchronization when needed.

Inventive Principle:
Principle #15Dynamics

3Reliability

If synchronization checks are performed before every input delivery to prevent false errors, then error handling reliability improves, but system complexity increases

Engineering Contradiction:
Improveerror handling accuracyVSAvoidsynchronization control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies self-service by implementing a self-check mechanism where the error handler automatically determines processor synchronization status before input delivery. The system monitors its own state and makes autonomous decisions about whether to deliver inputs or risk false error detections. This self-service approach maintains reliability without requiring complex external synchronization control mechanisms.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8171328B2State history storage for synchronizing redundant processors
Publication Date: 2012.05.01 TAHOE RES LTD
  • US8171328B2 patent drawing
  • US8171328B2 patent drawing
  • US8171328B2 patent drawing

AI summary

Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage.