Redundant Residue Arithmetic for Single-Digit Error Correction
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Solution Overview
Problem
Existing error detection and correction methods for arithmetic operations are complex and costly due to the need for multiple ALUs and increased latency, especially in high-speed applications, and are limited by the binary arithmetic system's inability to efficiently handle single digit errors in residue number systems.
Innovation Solution
The implementation of a residue number system (RNS) based error detection and correction method that uses carry-free arithmetic, allowing for continuous error detection and correction of single digit errors without propagating errors across digits, utilizing redundant RNS representations to maintain data integrity during integer and fixed-point arithmetic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triplication of ALU systems is used for error detection and correction, then reliability is improved, but device complexity and resource requirements increase significantly
Solution Approach 1:
The invention segments the error detection and correction function into separate dedicated circuitry that operates independently from the main ALU. Instead of requiring three full ALU systems, the patent uses a single ALU with accompanying error detection circuits that monitor and correct errors in real-time, dividing the functionality between computation and error handling components.
Solution Approach 2:
The patent introduces intermediate error detection and correction circuits that act as mediators between the ALU and the output. These intermediary components include parity check circuits and error correction logic that intercept and correct errors before they propagate, eliminating the need for multiple redundant ALU systems while maintaining reliability.
2Reliability
If triplication scheme is implemented for error detection and correction, then reliability is improved, but processing delay and latency increase
Solution Approach 1:
The invention implements preliminary error detection mechanisms that continuously monitor arithmetic operations as they occur. Parity check circuits are configured to detect errors during the computation process itself, and correction logic is pre-positioned to immediately correct detected errors without requiring post-processing or system re-synchronization, thus eliminating time delays.
Solution Approach 2:
The error detection and correction circuits operate continuously alongside the ALU operations, providing real-time monitoring and correction. This continuous operation ensures that errors are detected and corrected during the normal flow of computation without interrupting or pausing the processing, maintaining continuous useful action without time loss.
3Reliability
If binary arithmetic is used with traditional EDAC schemes, then error detection is possible, but single bit errors propagate to other bit positions
Solution Approach 1:
The invention extracts the error propagation problem by separating error detection and correction functions from the main arithmetic computation. Dedicated error detection circuits monitor the arithmetic results and identify errors before they can propagate to other bit positions, isolating the harmful effect and preventing its spread through the system.
Solution Approach 2:
The patent implements feedback mechanisms where error detection circuits continuously monitor ALU outputs and feed correction signals back to the computation process. When an error is detected in a bit position, the feedback logic immediately corrects it and prevents the erroneous value from being used in subsequent operations, stopping error propagation through the arithmetic chain.
Data Source
AI summary
A method and apparatus for detecting and correcting digit errors of arithmetic results and signed data represented in a redundant residue number system (RRNS) and further represented using a non-systematic method of complements suitable for processing by a complement based digital arithmetic of the full redundant range.