Redundant Scan Chains for IC Yield Improvement
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Solution Overview
Problem
Conventional scan design techniques face challenges in fault diagnosis due to combined scan design and combinational logic faults, leading to significant integrated circuit chip yield loss, as faults in scan chains can mask all scan cells, making it difficult to achieve high test coverage and resulting in yield losses of up to sixty percent.
Innovation Solution
Implementing a two-fold library of redundant latches and logic structures within integrated circuit scan chains, allowing for alternative paths to bypass faults and complete the scan design, with multiplexers enabling the selection between original and redundant paths for testing and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If scan design is implemented to reduce test pattern generation complexity, then test coverage is improved, but fault diagnosis becomes difficult and yield is reduced
Solution Approach 1:
The patent implements redundant scan chains that are copies of the original scan chains. When a fault is detected in the original scan chain, the redundant copy can be activated to bypass the faulty portion. This copying approach allows the system to maintain high test coverage while improving yield by providing alternative paths around defects, directly resolving the contradiction between test coverage and yield.
Solution Approach 2:
The patent incorporates redundant scan chains during the design phase as a preventive measure against potential faults. This beforehand cushioning ensures that if defects are present in the original scan chain, the redundant paths are already in place to compensate, thus maintaining both high test coverage and yield without requiring post-manufacturing repairs.
2Reliability
If redundant latches and logic structures are added to create alternative paths, then yield is improved, but device complexity increases
Solution Approach 1:
The redundant scan chains are designed to be multi-functional: they serve as backup paths for fault bypass, can be activated selectively based on test results, and maintain the same structural characteristics as the original chains. This universality allows the system to improve yield through redundancy while managing complexity by using standardized, interchangeable components rather than custom complex circuits.
Solution Approach 2:
The system dynamically switches between original and redundant scan chains based on detected faults. The complexity is managed through dynamic activation rather than permanent engagement of all redundant components, allowing the system to maintain simplicity during normal operation while providing complexity only when needed for fault tolerance, thus improving yield without permanently increasing operational complexity.
Data Source
AI summary
Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.