Redundant SRAM Array With Different Cell Topology
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Solution Overview
Problem
Existing RAM memory systems lack an effective method to provide redundancy without compromising speed or increasing integrated circuit area, especially when dealing with cell failures, as they often use redundant cells with the same design, which may not enhance reliability or efficiency.
Innovation Solution
Implementing a RAM memory system with a redundant array of memory cells having a different designed cell circuit topology, such as using 6T SRAM cells for the main array and 8T or 12T SRAM cells for the redundant array, along with a content addressable memory (CAM) to detect and address failed cells, allowing for efficient data storage and retrieval while maintaining system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant memory cells with the same design as main array cells are used, then circuit area is minimized, but reliability is not improved and failure modes are not diversified
Solution Approach 1:
The patent applies local quality by using different cell circuit topologies for redundant cells compared to main array cells. Specifically, the main array uses 6T SRAM cells while the redundant array uses 8T or 12T SRAM cells with enhanced stability and lower failure rates. This localized differentiation in cell structure provides improved reliability for critical backup functions without requiring all cells in the system to use the more complex topology.
Solution Approach 2:
The patent changes key parameters of the memory cell design by transitioning from 6-transistor to 8-transistor or 12-transistor configurations for redundant cells. This parameter change increases the stability margin and reduces susceptibility to manufacturing variations and process deviations, thereby improving reliability while accepting increased device complexity only where necessary for backup functions.
2Productivity
If faster read operations are implemented, then productivity increases, but voltage requirements increase which reduces energy efficiency
Solution Approach 1:
The patent applies local quality by using different cell topologies optimized for specific functions: 6T cells for main array storage and 8T/12T cells for redundant array with enhanced read stability. The redundant cells are designed to operate reliably at lower voltages while maintaining fast read speeds, thus improving productivity without proportionally increasing voltage requirements and energy consumption.
Solution Approach 2:
The patent uses a composite approach by combining multiple cell types (6T, 8T, 12T) within the same memory system, each optimized for specific performance characteristics. This composite structure allows the system to achieve fast read operations through the main array while the redundant array provides reliable backup at lower voltage, thus balancing productivity and energy efficiency.
Data Source
AI summary
A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.