Concurrent Redundant Via Insertion and Timing Optimization
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Solution Overview
Problem
Conventional techniques for inserting redundant vias in integrated circuit (IC) chip design are ad-hoc and do not adequately address manufacturing yield, often requiring additional timing optimization due to changes in resistance and capacitance, and typically perform redundant via insertion after timing optimization, which can increase design convergence time and lead to suboptimal results.
Innovation Solution
A system that concurrently performs redundant via insertion and timing optimization during the IC chip design routing process, using soft rules to reserve space for redundant vias and iteratively adjusting the routing solution to incorporate timing effects, allowing for a higher number of redundant vias to be inserted while maintaining design rule compliance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant via insertion is performed after timing optimization using conventional ad-hoc techniques, then manufacturing yield is improved, but design convergence time increases and timing optimization must be repeated due to changes in resistance and capacitance
Solution Approach 1:
The patent merges redundant via insertion and timing optimization into a single concurrent process. The router simultaneously performs routing, inserts redundant vias, and optimizes timing in one integrated pass, eliminating the need for sequential execution and repeated timing optimizations. This combination resolves the contradiction by achieving both high manufacturing yield and fast design convergence.
Solution Approach 2:
The patent performs preliminary timing optimization before redundant via insertion within the same routing pass. By anticipating timing effects and performing preliminary optimization, the system avoids repeated timing passes that would otherwise be required after redundant via insertion, thus reducing overall design convergence time while maintaining manufacturing yield benefits.
2Reliability
If redundant vias are inserted to improve manufacturing yield, then yield increases, but the resistance and capacitance of circuit elements change requiring additional timing optimization
Solution Approach 1:
The patent combines redundant via insertion and timing optimization into a unified concurrent process. By integrating these two functions that were previously separate and sequential, the system handles resistance and capacitance changes from redundant vias automatically within the same pass, avoiding additional timing optimization complexity.
Solution Approach 2:
The patent maintains continuous timing optimization throughout the routing process rather than performing discrete, separate timing passes. The timing optimization continuously adapts as redundant vias are inserted, ensuring that resistance and capacitance changes are immediately accounted for without requiring additional optimization cycles.
3Reliability
If conventional ad-hoc redundant via insertion techniques are used, then some redundant vias are added, but insufficient number of vias are inserted and space constraints prevent optimal via placement
Solution Approach 1:
The patent uses dynamic space reservation during routing where the available space for redundant vias is continuously updated based on current routing decisions. This dynamic approach allows the system to identify and reserve optimal locations for redundant vias throughout the routing process, maximizing the number of vias that can be inserted while maintaining design rule compliance.
Solution Approach 2:
The patent implements feedback mechanisms where the router continuously monitors space availability and adjusts routing decisions to accommodate redundant via insertion. The system uses feedback from space constraints to modify routing paths and via placements, ensuring optimal redundant via placement that maximizes manufacturing yield without violating design rules.
Data Source
AI summary
One embodiment of the present invention provides a system that concurrently performs redundant via insertion and timing optimization during routing of an integrated circuit (IC) chip design. During operation, the system performs an initial routing on the IC chip design to obtain a routing solution, which includes a set of vias. The system then performs a redundant-via-insertion operation on the routing solution, wherein the redundant-via-insertion operation attempts to modify a via within the set of vias into a redundant via. Next, the system performs a timing optimization on the routing solution by iteratively: (1) performing a timing analysis on the routing solution; (2) performing a logic optimization on the routing solution; and (3) performing an incremental routing adjustment on the routing solution, wherein the incremental routing adjustment adjusts the redundant vias.