Redundant Via Pairs for Memory Bit Read Reliability
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Solution Overview
Problem
High resistance in vias within memory arrays can lead to read errors due to slowed discharge rates, particularly at low operating temperatures, affecting the reliability of memory bit operations in integrated circuits.
Innovation Solution
The implementation of redundant vias in parallel with existing vias to create redundant via pairs, which maintain low resistance paths and prevent read errors without increasing the area of memory cells, thereby ensuring reliable data read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant vias are added in parallel with existing vias, then reliability of read operations is improved, but device complexity increases
Solution Approach 1:
The via structure is segmented into multiple parallel vias (first via and second via) instead of using a single via. This segmentation provides redundancy so that if one via has high resistance, the other can compensate, improving read operation reliability without significantly increasing overall cell area.
Solution Approach 2:
Redundant vias are incorporated into the memory cell design beforehand to cushion against potential via failures or high resistance conditions. This preventive approach ensures that even if one via performs poorly, the memory cell can still function correctly, addressing reliability issues before they manifest as failures.
2Reliability
If memory cell area is increased to accommodate redundant vias, then reliability is improved, but area of memory cell increases
Solution Approach 1:
The first via and second via are merged into a compact via pair structure that fits within the existing memory cell footprint. The vias are positioned adjacent to each other and share common routing paths where possible, allowing the redundant structure to be integrated without proportionally increasing the memory cell area.
Solution Approach 2:
The redundant vias are arranged in a two-dimensional configuration (side-by-side adjacent vias) rather than stacking them vertically or spreading them out horizontally. This dimensional arrangement optimizes space utilization and minimizes the area overhead while maintaining the redundancy benefit.
Data Source
AI summary
An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.