Reed-Solomon Burst Decoder for Single-Device Memory Failures
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Solution Overview
Problem
Existing ECC techniques struggle to efficiently detect and correct errors due to entire memory device failures or single device failures, leading to uncorrectable errors and increased costs due to the need for additional parity bits, which also reduces media capacity and increases power usage.
Innovation Solution
Implementing a single-pass Reed-Solomon (RS) coding scheme with a modified Berlekamp-Massey Algorithm (BMA) and Wu technique for burst error correction, leveraging the assumption that errors are confined to a single DRAM component, reducing the search space for error locations and requiring fewer parity symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chipkill ECC techniques are used to correct entire device failures, then reliability is improved, but parity bit requirements increase significantly
Solution Approach 1:
The patent segments the error correction problem by distinguishing between different error types (single-device failures versus multi-device failures) and applying different correction strategies. The RS code is configured to handle single-device failures with minimal parity bits, while multi-device failures are managed through detection and retry mechanisms rather than full correction.
Solution Approach 2:
The patent applies partial correction by focusing resources on correcting the most common failure mode (single-device failures) rather than attempting to correct all possible failure patterns. The RS code parameters are optimized to correct t errors where t corresponds to single-device failure scenarios, providing sufficient reliability improvement without the excessive parity overhead of chipkill techniques designed for broader failure coverage.
2Reliability
If more parity bits are added to correct errors, then reliability is improved, but media capacity decreases
Solution Approach 1:
The patent changes the parameters of the Reed-Solomon code to optimize the balance between error correction capability and media capacity. By selecting specific values for code length n and error correction capability t based on the actual failure characteristics of the memory system, the patent achieves adequate reliability with minimal overhead, preserving maximum media capacity for useful data storage.
3Reliability
If more parity bits are added to correct errors, then reliability is improved, but power usage increases
Solution Approach 1:
The patent optimizes the RS code parameters to use the minimum necessary parity bits for achieving the target reliability level. By carefully selecting t (error correction capability) based on actual failure rates rather than using excessive correction capability, the patent reduces the number of parity bits required, thereby reducing the computational power consumption during encoding and decoding operations.
4Device complexity
If standard RS decoding is used, then implementation is simpler, but burst errors from single device failures cannot be efficiently corrected
Solution Approach 1:
The patent performs preliminary identification of burst error patterns by analyzing the syndrome structure before applying full decoding. When burst errors are detected (indicating single-device failures), the system activates the optimized BEC decoding path. This preliminary action allows the system to maintain simple standard RS decoding for normal cases while enabling sophisticated burst correction only when needed, balancing complexity and reliability.
Data Source
AI summary
Provided is an apparatus comprising a search engine that (i) receives parallel input of a set of syndrome polynomial products corresponding to a set of ECC words and (ii) produces corresponding sets of polynomial roots therefrom and a sequence detector that identifies sequences within each of the polynomial roots within the set of roots. The apparatus also includes a sequence check logic that (i) combines the identified sequences within each of the polynomial roots and (ii) performs a sequence check of the combined identified sequences to determine whether only one of the identified sequences is valid; and an error location generator that derives an error location in each of the ECC words within the set responsive to the valid sequence.