Programmable Reed-Solomon Decoder for Lower-Complexity Error Correction
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Solution Overview
Problem
Existing integrated circuit technologies face challenges in efficiently implementing forward error correction techniques, which can render integrated circuits unusable due to corrupted data, and these techniques often result in significant limitations and complexity in data processing.
Innovation Solution
A decoder system comprising a memory with program code for generating control signals, an address generator, and data processing circuits that produce error correction values, including error evaluator and locator signals, utilizing Reed-Solomon decoders for efficient error correction, and a method involving a programmable integrated circuit architecture with pipelining stages to handle error correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If forward error correction techniques are implemented in integrated circuits, then data reliability is improved, but device complexity increases significantly
Solution Approach 1:
The decoder is divided into multiple specialized data processing circuits, each handling specific error correction functions. This segmentation allows complex error correction to be performed through coordinated simple operations in each circuit, improving reliability while managing device complexity through functional decomposition.
Solution Approach 2:
Syndrome data is pre-calculated and stored before the actual error correction process. This preliminary action allows the decoder to quickly identify and correct errors without performing complex calculations during the critical data recovery phase, thereby improving reliability while keeping the main decoding circuitry relatively simple.
2Reliability
If multiple data processing circuits are used for error correction, then error correction capability is improved, but manufacturing cost increases
Solution Approach 1:
The multiple data processing circuits are designed with universal functionality, where each circuit can handle different aspects of error correction using similar architectural patterns. This multi-functionality allows for standardized manufacturing processes and reduces overall manufacturing cost despite the presence of multiple circuits, as they can be produced using the same fabrication techniques and design methodologies.
3Productivity
If Reed-Solomon decoders are implemented, then error correction efficiency is improved, but resource requirements increase
Solution Approach 1:
Multiple Reed-Solomon decoding functions are merged into a unified decoder architecture that shares common resources such as syndrome calculation units, error location polynomial generators, and error magnitude calculators. This merging approach maintains high error correction efficiency by performing all necessary operations in a coordinated manner while reducing overall resource requirements through resource sharing and elimination of redundancies.
Data Source
AI summary
A decoder in a device receiving data having an error correction code is described. The decoder comprises a memory storing program code having instructions including control signals for decoding an error correction code; an address generator coupled to the memory, the address generator updating an address coupled to the memory for generating a next control signal; and a data processing circuit coupled to receive an instruction from the memory and further coupled to receive syndrome data, the data processing circuit generating error correction values. A method for decoding data having an error correction code is also disclosed.