Reed-Solomon Soft-Decision Decoding with Parity-Based Erasure Control

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Solution Overview

Problem

Reed-Solomon code soft-decision decoding methods face a challenge in reducing decoding time while minimizing the degradation of error correction performance, particularly in applications like phase change memory where quick decoding is required.

Innovation Solution

The proposed solution involves a Reed-Solomon code soft-decision decoding device and method that includes a syndrome generation circuit, a key equation solver circuit, a Chien-search & error-evaluator circuit, a decoding error detection circuit, and an erasure control circuit, which determine the number of errors as odd or even to provide specific erasure patterns, allowing for efficient decoding by prioritizing symbols with low reliability for erasure correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of iterations of decoding is increased to improve error correction performance, then the error correction performance is improved, but the decoding time is greatly increased

Engineering Contradiction:
Improveerror correction performanceVSAvoiddecoding time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by determining the parity of error count before executing the full iterative decoding process. The erasure control circuit predicts whether the error count is odd or even and pre-selects the appropriate erasure pattern (first pattern for odd, second pattern for even), allowing the decoder to skip unnecessary iterations and directly apply the correct correction strategy, thus reducing decoding time while maintaining error correction performance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamics by making the decoding process adaptive based on error parity detection. The system dynamically switches between two different erasure patterns depending on the detected error parity, allowing the decoding algorithm to adjust its behavior in real-time based on the actual error conditions, thereby optimizing both speed and accuracy

Inventive Principle:
Principle #15Dynamics

2Loss of time

If the number of iterations of decoding is reduced to reduce decoding time, then the decoding time is reduced, but the error correction performance is degraded

Engineering Contradiction:
Improvedecoding timeVSAvoiderror correction performance
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

By performing error parity detection beforehand and pre-selecting the appropriate erasure pattern, the system ensures that the correct decoding strategy is applied from the start. This preliminary action eliminates the need for multiple trial iterations, allowing single-pass or reduced-iteration decoding to achieve the same error correction performance that would otherwise require many more iterations

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses feedback from the error parity detection circuit to control the selection of erasure patterns. The decoding error detection circuit provides feedback about the error conditions, and this feedback is used by the erasure control circuit to select the appropriate pattern, creating a closed-loop system that ensures correct decoding with minimal iterations

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20220140845A1Reed-solomon code soft-decision decoding method and device
Publication Date: 2022.05.05 SK HYNIX INC
  • US20220140845A1 patent drawing
  • US20220140845A1 patent drawing
  • US20220140845A1 patent drawing

AI summary

Disclosed is an erasure-based Reed-Solomon code soft-decision decoding method and device, capable of reducing a decoding time while minimizing the effect on error correction performance. The Reed-Solomon code soft-decision decoding device includes an erasure control circuit configured to determine whether a number of errors in a codeword is odd or even, and to provide a key equation solver circuit with a first erasure pattern or a second erasure pattern according to a result of the determining when a decoding failure is detected by a decoding error detection circuit, the first erasure pattern being provided when the number of errors is odd, the second erasure pattern being provided when the number of errors is even.