Pipelined Reed-Solomon List Decoding for Faster Soft Error Correction

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Solution Overview

Problem

Reed-Solomon error-correction codes (RS ECC) face challenges in modern applications due to their complexity and resource requirements, particularly in completing decoding operations within time and resource constraints in devices with stringent allowances.

Innovation Solution

The implementation of a hard Reed-Solomon ECC decoder capable of correcting up to t=(n−k)/2 symbols, with a soft decoder capable of correcting more than t errors using soft-information, employing a pipelined architecture with iterative decoding and syndrome modification circuits to reduce memory usage and improve processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Reed-Solomon ECC decoding is implemented with high error correction capability, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoder complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The decoder is divided into multiple pipeline stages, each handling specific decoding operations. This segmentation allows parallel processing of different aspects of the decoding algorithm, improving throughput while maintaining manageable complexity in each individual stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The decoder implements dynamic resource allocation through pipelining, where processing resources are dynamically utilized across multiple stages. This allows the system to achieve high error correction capability without proportionally increasing overall complexity, as each stage operates independently with optimized resource usage.

Inventive Principle:
Principle #15Dynamics

2Productivity

If Reed-Solomon ECC decoding is completed within stringent time allowances, then productivity is improved, but manufacturing precision deteriorates

Engineering Contradiction:
Improvedecoding speedVSAvoiddecoding accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The decoding process is segmented into multiple pipeline stages that can operate concurrently. This allows the system to process multiple codewords simultaneously at different stages of decoding, achieving high throughput without sacrificing the accuracy of individual decoding operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The decoder performs preliminary error detection and syndrome calculation in early pipeline stages before committing to full decoding. This preliminary action allows the system to quickly identify and handle erroneous codewords, improving overall productivity while maintaining precision through subsequent verification stages.

Inventive Principle:
Principle #10Preliminary action

3Loss of substance

If memory requirements for RS ECC decoding are reduced, then loss of substance is improved, but device complexity increases

Engineering Contradiction:
Improvememory usageVSAvoiddecoder architecture
Core Design Contradiction:
Loss of substanceVSDevice complexity

Solution Approach 1:

The decoder employs dynamic memory management where buffer sizes and storage requirements are optimized based on the specific pipeline stage and current processing needs. This dynamic approach reduces overall memory requirements while maintaining the necessary data for accurate decoding operations.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The decoder transitions from storing all intermediate decoding data in memory to processing data through time-based pipeline stages. By moving data through the system in a sequential flow across multiple stages rather than storing it all simultaneously, the system reduces memory requirements while maintaining decoding capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7454690B1Architecture and control of reed-solomon list decoding
Publication Date: 2008.11.18 MARVELL ASIA PTE LTD
  • US7454690B1 patent drawing
  • US7454690B1 patent drawing
  • US7454690B1 patent drawing

AI summary

Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.