Reed-Solomon Encoder Circuit Using LU Decomposition for High-Speed Links
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Solution Overview
Problem
Existing Reed-Solomon encoding techniques based on polynomial division suffer from increased critical path complexity with parallel input, leading to decreased encoder operational frequency, which is inadequate for high-speed communication systems like 100G Ethernet or 400G Ethernet.
Innovation Solution
The implementation of a Reed-Solomon encoder circuit that utilizes LU decomposition and parallel processing to efficiently compute parity check symbols, allowing for pipelining and improved error correction capabilities, including the use of linear equation solver circuits for forward and backward substitutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polynomial division method is used for Reed-Solomon encoding, then check symbols can be calculated based on input of data symbols, but the critical path grows with each additional parallel input symbol and encoder operational frequency decreases
Solution Approach 1:
The patent segments the Reed-Solomon encoding process into multiple independent parallel paths, where each path processes a portion of the data symbols simultaneously. This segmentation breaks the sequential dependency inherent in polynomial division, allowing multiple operations to occur in parallel without increasing critical path complexity, thereby maintaining high encoder operational frequency.
Solution Approach 2:
The patent transforms the traditional single-dimension sequential polynomial division approach into a multi-dimensional parallel processing architecture. By introducing additional processing dimensions through parallel computation paths and reorganizing the data flow, the system achieves higher throughput without proportionally increasing the critical path length, thus resolving the frequency-complexity tradeoff.
2Productivity
If substitution method is used to calculate check symbols based on multiple data symbols at once, then processing efficiency improves, but the feedback nature causes critical path to grow and operational frequency to decrease
Solution Approach 1:
The patent extracts and eliminates the feedback mechanism from the encoding process. Instead of using substitution methods that require iterative feedback to compute check symbols, the invention employs a direct feedforward computation approach where check symbols are calculated in a single pass without feedback loops, thereby maintaining processing efficiency while avoiding critical path growth.
Solution Approach 2:
The patent performs preliminary preparation of computation constants and pre-computes certain intermediate values before the main encoding operation. By preparing these elements in advance, the actual encoding process can proceed with simpler, non-iterative operations that do not require feedback paths, thus achieving high processing efficiency without increasing operational complexity.
Data Source
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AI summary
The present embodiments relate to Reed-Solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A Reed-Solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. The Reed-Solomon encoder circuit may further compute parity check symbols by solving a system of linear equations that includes the partial syndrome vector and a second matrix. As an example, the second matrix may be decomposed into a lower triangular matrix and an upper triangular matrix, and the parity check symbols may be computed by performing a forward substitution and a backward substitution using the lower and upper triangular matrices. The Reed-Solomon encoder circuit may generate a Reed-Solomon code word by combining the data symbols and the parity check symbols, and provide the Reed-Solomon code word at an output port.