Reed-Solomon Burst Decoding for Single-Device Memory Failures
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Solution Overview
Problem
Existing ECC techniques struggle to efficiently detect and correct errors due to memory device failures, particularly when an entire device fails or all bits in a given read from a single device are corrupted, leading to uncorrectable errors and increased reliability risks.
Innovation Solution
The proposed solution involves constructing two codewords from a single cacheline, with the first codeword having sufficient parity to correct a single device failure and the second codeword not. Error locations from the first codeword are used to mark erasures in the second codeword, enabling correction of a single device in both codewords. Additionally, a collaborative interleaved Reed-Solomon decoding technique is used to enable beyond half-minimum distance bounds correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chipkill ECC techniques are used to correct entire device failures, then reliability is improved, but parity bit requirements increase significantly
Solution Approach 1:
The patent segments the error correction problem into two distinct codewords: a first codeword with sufficient parity for single-device correction and a second codeword with reduced parity. This segmentation allows the system to achieve device failure correction without requiring the full parity overhead of traditional chipkill techniques across the entire code structure.
Solution Approach 2:
The patent applies local quality by providing different levels of error correction capability to different portions of the data. The first codeword receives enhanced parity protection specifically targeted at device failure scenarios, while the second codeword uses standard or reduced parity, optimizing the overall parity bit requirements while maintaining reliability.
2Quantity of substance
If conventional ECC techniques are used that cannot detect entire device failures, then parity bit requirements are reduced, but uncorrectable errors increase
Solution Approach 1:
The patent performs preliminary error detection and location using the first codeword with sufficient parity before attempting correction with the second codeword. Error locations from the first codeword are used to mark erasures in the second codeword, enabling the system to identify and handle device failures proactively rather than reactively.
Solution Approach 2:
The first codeword acts as an intermediary that bridges the gap between reduced-parity and full-chipkill approaches. It provides the necessary error location information that enables the second codeword to achieve device failure correction with fewer total parity bits than traditional chipkill methods.
3Reliability
If multi-pass or multiple decoding attempt approaches are used, then correction capability is improved, but latency and overhead increase
Solution Approach 1:
The patent merges the error detection and correction functions into a unified two-codeword structure that can be processed in a single decoding pass. By combining the strengths of high-parity and low-parity codes in a collaborative interleaved Reed-Solomon decoding framework, the system achieves multi-pass level correction capability without the iterative latency overhead.
Solution Approach 2:
The patent applies partial action by using the first codeword's error location information selectively to mark only the erasures that need correction in the second codeword, rather than performing full iterative decoding attempts. This targeted approach reduces the computational overhead and latency associated with multiple decoding passes.
Data Source
AI summary
Provided is an apparatus comprising a search engine configured to (i) receive parallel input of a set of syndrome polynomial products corresponding to a set of ECC words and (ii) produce corresponding sets of polynomial roots therefrom and a sequence detector configured to identify sequences within each of the polynomial roots within the set of roots. Also provided is sequence check logic for (i) combining the identified sequences within each of the polynomial roots and (ii) performing a sequence check of the combined identified sequences to determine whether only one of the identified sequences if valid; and an error location generator to derive an error location in each of the ECC words within the set responsive to the valid sequence.