Pipelined Reed-Solomon Decoder for Low-Latency High Throughput
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Solution Overview
Problem
Conventional Reed Solomon decoders suffer from long latency and low throughput due to their sequential operation, which restricts high-speed decoding capabilities and prevents simultaneous processing of new codewords during ongoing decoding operations.
Innovation Solution
The implementation of a pipelined Reed Solomon decoder with multiple sub-KES circuits, a syndrome calculation circuit, and a Chien search and error evaluation circuit, allowing for parallel processing stages that reduce latency and enable concurrent decoding of new codewords.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional Reed Solomon decoder is used with sequential operation, then the decoding operation is completed accurately, but the latency becomes long and throughput is low
Solution Approach 1:
The KES circuit is divided into multiple sub-KES circuits (first sub-KES circuit, second sub-KES circuit, etc.) that process different portions of the syndrome separately. This segmentation allows parallel processing of the key equation solution, reducing the overall latency from 2t clock cycles to approximately t clock cycles while maintaining decoding accuracy
Solution Approach 2:
The decoder is transformed from a static sequential structure to a dynamic pipelined structure where multiple decoding stages can operate simultaneously at different clock cycles. The pipeline allows new codewords to be decoded every 2 clock cycles after the initial latency period, dynamically increasing throughput
2Productivity
If the decoder operates sequentially to ensure accurate decoding, then decoding correctness is maintained, but new codewords cannot be processed during ongoing decoding operations
Solution Approach 1:
The decoder employs a pipelined architecture where the syndrome calculation circuit, sub-KES circuits, and CSEE circuits operate in sequential stages that overlap in time. This dynamic pipeline structure enables continuous processing of multiple codewords through the system, with each stage working on different codewords at different clock cycles, thereby increasing throughput without sacrificing decoding accuracy
Solution Approach 2:
The decoder is segmented into distinct functional blocks (syndrome calculation, key equation solving with multiple sub-KES circuits, and error location/evaluation) that can operate independently in parallel. This modular segmentation allows each segment to be optimized separately and enables the pipeline operation that processes new codewords concurrently with ongoing decoding operations
Data Source
AI summary
A Reed Solomon decoder may include a syndrome calculation (SC) circuit, a key equation solver (KES) circuit, and a Chien search and error evaluation (CSEE) circuit. The SC circuit calculates a syndrome from a codeword. The KES circuit includes a plurality of sub-KES circuit and calculates an error location polynomial and an error evaluation polynomial from the syndrome. The CSEE circuit calculates an error location and an error value from the error location polynomial and the error evaluation polynomial. Each of the plurality of sub-KES circuits, the SC circuit and the CSEE circuit respectively constitute pipeline stages. The Read Solomon decoder may also include a FIFO queue that queues the codeword among a plurality of codewords sequentially received, and an error correction circuit that produces error corrected data using an output from the FIFO queue, the error location, and the error value.