Reenter Queue Loop Control for Multi-Threaded Reconfigurable Fabric
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Solution Overview
Problem
Existing computing systems face limitations in performance and energy efficiency for compute-intensive tasks such as Fast Fourier Transforms and finite impulse response filters, particularly in applications like artificial intelligence and 5G technologies, where dynamic reconfiguration and self-scheduling are needed.
Innovation Solution
A multi-threaded, coarse-grained configurable computing architecture with dynamic self-configuration and self-reconfiguration capabilities, utilizing a reenter queue for loop execution control, conditional branching, and asynchronous signaling to optimize thread execution and energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing computing systems are used for compute-intensive tasks, then basic computation can be performed, but performance and energy efficiency are insufficient
Solution Approach 1:
The patent implements dynamic reconfiguration of the computing fabric, allowing the system to adapt its architecture runtime based on computational requirements. The reconfigurable logic enables the computing system to transform its structure dynamically, optimizing performance for different compute-intensive workloads while managing energy consumption efficiently.
Solution Approach 2:
The system changes operational parameters including thread configuration, dataflow patterns, and resource allocation dynamically. By adjusting these parameters based on workload characteristics, the system optimizes both computation performance and energy efficiency for different applications.
2Adaptability or versatility
If dynamic reconfiguration is implemented, then adaptability improves, but system complexity increases
Solution Approach 1:
The computing system is divided into modular computing elements that can be independently configured and reconfigured. This segmentation allows complex reconfiguration tasks to be broken down into manageable units, reducing overall system complexity while maintaining high adaptability.
Solution Approach 2:
The patent creates a universal reconfigurable computing fabric where the same hardware structure can perform multiple functions through configuration changes. This multi-functionality reduces the need for specialized components, thereby managing complexity while enhancing adaptability across different applications.
3Productivity
If self-scheduling is implemented, then execution efficiency improves, but control mechanism complexity increases
Solution Approach 1:
The computing fabric implements self-scheduling capabilities where threads automatically manage their own execution without external intervention. This self-service approach allows efficient thread execution while reducing the complexity of centralized control mechanisms, as the system manages itself through inherent scheduling logic.
4Speed
If loop execution with reenter queue is implemented, then loop processing speed improves, but queue management complexity increases
Solution Approach 1:
The reenter queue serves as an intermediary structure that simplifies loop execution management. By introducing this intermediate data structure, the system achieves fast loop processing while offloading the complexity of iteration management to the queue mechanism, rather than requiring complex control logic in the computing elements themselves.
Data Source
AI summary
Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.