Reentrant Via Bottom Structure for Electromigration-Resistant Interconnects

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Solution Overview

Problem

Integrated circuit (IC) devices face reliability issues due to increasing current densities, leading to unpredictable electromigration failures in interconnects, which necessitate excessive design margins and limit allowable current densities.

Innovation Solution

Implementing a reentrant via structure with a flared bottom in the interconnects, characterized by a dielectric angle greater than 90 degrees, to minimize current density changes and reduce electromigration effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional via structures are used, then manufacturing is simpler, but electromigration failures occur unpredictably early due to high current densities

Engineering Contradiction:

Improveinterconnect reliabilityVSAvoidvia structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The via structure employs a reentrant profile with curved sidewalls that flare outward at the bottom, creating a non-linear geometric shape. This curvature redistributes the current density pathway, avoiding sharp corners and concentrating current flow in a more uniform manner through the via, thereby reducing electromigration effects and improving interconnect reliability

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

The via structure features different geometric characteristics at different locations: the upper portion has a narrower width while the bottom portion flares outward to a wider width. This local variation in geometry optimizes the current density distribution specifically at the via bottom where electromigration is most severe, while maintaining appropriate via dimensions in the upper regions for electrical performance

Inventive Principle:

Principle #3Local quality

2Reliability

If design margins are increased to account for unpredictable failures, then reliability is improved, but allowable current densities are severely limited

Engineering Contradiction:

Improveinterconnect reliabilityVSAvoidallowable current density

Core Design Contradiction:

ReliabilityVSPower

Solution Approach 1:

The reentrant via profile converts the potentially harmful concentration of current at sharp via corners into a beneficial uniform current distribution. By designing the via with flared bottom sidewalls, the structure naturally redirects current flow to follow the curved profile, transforming what would be a failure-inducing geometry into a reliability-enhancing feature that allows higher current densities without excessive design margins

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If via bottom width is reduced to minimize electromigration, then electromigration effects are reduced, but manufacturing precision requirements increase

Engineering Contradiction:

Improveelectromigration resistanceVSAvoidvia bottom width control

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

Instead of reducing the via bottom width to minimize electromigration, the invention inverts the conventional approach by flaring the via bottom to a wider width. This inverted geometry achieves the opposite effect: it reduces current density by providing a larger cross-sectional area at the via bottom where current concentration is most problematic, while the reentrant profile maintains smooth transitions that facilitate manufacturing

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS20250300051A1Interconnect structure with reentrant via bottom sidewall

Publication Date: 2025.09.25 INTEL CORP

AI summary

Interconnect structures having reentrant sidewalls at via bottoms. A via may be over and coupled to a metallization layer, extending through upper and lower dielectric layers over the metallization layer, and having a reentrant sidewall in the thinner, lower dielectric layer. The via may have a narrower width level with an interface of the upper and lower dielectric layers. The via may couple to a second metallization layer over the via, and the via may have a reentrant sidewall adjacent the upper metallization layer. The via structure may be in a bridge die, interposer, IC die, etc.