Reference ADC Background Calibration for Time-Interleaved Mismatch
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (I-ADCs) face challenges in high-precision, high-speed sampling due to channel-to-channel mismatch errors such as timing skew, gain, and static non-linearity, which are exacerbated by environmental changes, making effective calibration difficult.
Innovation Solution
The introduction of a reference ADC that samples the input signal in a predetermined timing relationship with sub-ADCs allows for the comparison of outputs, correlating mismatch errors with known signatures to generate correction signals that minimize channel-to-channel mismatch errors through a digital calibration block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple parallel ADC channels are used to increase sampling rate, then productivity is improved, but device complexity increases due to multiple channels introducing component errors such as phase shift errors
Solution Approach 1:
The patent implements a feedback mechanism where the digital output of each ADC channel is fed back to a calibration circuit. The calibration circuit generates correction signals based on the detected mismatch errors and feeds them back to adjust the ADC channels, thereby reducing timing skew and gain mismatch while maintaining high sampling rates
Solution Approach 2:
The patent introduces an intermediary calibration circuit that mediates between the multiple ADC channels. This calibration circuit detects mismatch errors and generates correction signals that are applied to the ADC channels, serving as an intermediary mechanism to coordinate and synchronize the multiple channels without requiring complex direct inter-channel control
2Measurement precision
If calibration is performed to reduce mismatch errors, then measurement precision is improved, but loss of time occurs due to calibration process interruption
Solution Approach 1:
The patent enables continuous calibration by performing mismatch error detection and correction in the background during normal ADC operation. The calibration process does not interrupt the useful conversion function, as the calibration signals are injected through dedicated calibration inputs while the main conversion continues uninterrupted on the data path
Solution Approach 2:
The patent performs preliminary calibration by detecting mismatch errors and generating correction signals before they significantly degrade measurement precision. The calibration circuit continuously monitors and adjusts the ADC channels in advance, preventing error accumulation that would require time-consuming re-calibration
3Productivity
If background calibration is implemented without interrupting conversion, then productivity is maintained, but device complexity increases due to additional calibration circuitry
Solution Approach 1:
The patent segments the calibration function from the main conversion path by providing separate calibration inputs and using dedicated calibration circuitry that operates independently. This allows calibration to be performed on specific ADC channels or groups without affecting the overall conversion productivity of the I-ADC system
Solution Approach 2:
The patent implements a universal calibration circuit that can calibrate multiple ADC channels using a single calibration infrastructure. The calibration circuit generates correction signals that can be applied to any or all ADC channels, providing multi-functional capability that reduces the need for separate calibration circuits for each channel
Data Source
AI summary
Various embodiments allow for background calibration of channel-to-channel mismatch errors. In certain embodiments calibration is accomplished by comparing the output of I-ADCs against the output of a reference ADC and correlating the difference to a known function to obtain a correction signal that can be used to correct channel-to-channel mismatch errors.