Reference ADC Sampling Shift for Timing-Skew Calibration
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Solution Overview
Problem
Conventional time-interleaved ADCs suffer from offset, gain, and timing mismatches due to the alignment of sampling timing between sub-DACs, which introduces side effects like spurs, necessitating a novel calibration method that avoids these issues.
Innovation Solution
The proposed solution involves using a reference ADC with sampling point shifting, where the sampling clocks of the reference and main ADCs have the same frequency but different phases, employing a sampling control circuit to delay the reference clock and a compensation circuit to adjust digital outputs, followed by a hybrid calibration circuit for timing-skew correction, combining digital and analog corrections to align sampling timings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling timing of the reference ADC is aligned with that of the main ADC for calibration, then timing-skew calibration can be performed, but the reference ADC will pull or disturb the sampling network and cause spurs
Solution Approach 1:
Instead of aligning the reference ADC sampling timing with the main ADC (conventional approach), the patent inverts the approach by intentionally misaligning the reference ADC sampling timing to be different from the main ADC sampling timing. This inversion prevents the reference ADC from disturbing the main ADC's sampling network while still enabling timing-skew calibration through comparison of the misaligned samples.
2Productivity
If a time-interleaved ADC structure is used to achieve high-speed and high-resolution conversion, then performance requirements are met, but offset, gain, and timing mismatches occur between sub-DACs
Solution Approach 1:
The patent employs self-service by using the reference ADC to automatically calibrate the main ADC's timing skew without requiring external calibration equipment or complex calibration circuits. The reference ADC serves itself and the main ADC through the misaligned sampling comparison method, enabling autonomous correction of timing mismatches in the time-interleaved structure.
3Measurement precision
If conventional calibration methods are used with aligned sampling timing, then calibration can be performed, but area penalties increase and cost efficiency decreases
Solution Approach 1:
The patent applies universality by designing a single reference ADC that can calibrate multiple main ADCs in a time-interleaved system. The misaligned sampling method allows one reference ADC to serve multiple calibration functions simultaneously, reducing the overall calibration circuit area and improving cost efficiency compared to conventional methods that require separate calibration paths for each ADC.
Data Source
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AI summary
An analog-to-digital converter (ADC) system includes a main ADC, a reference ADC, a sampling control circuit, and a calibration circuit. The main ADC obtains a first sampled input voltage by sampling an analog input according to a first sampling clock, and performs analog-to-digital conversion upon the first sampled voltage to generate a first sample value. The reference ADC obtains a second sampled voltage by sampling the analog input according to a second sampling clock, and performs analog-to-digital conversion upon the second sampled voltage to generate a second sample value. The sampling control circuit controls the second sampling clock to ensure that the second sampling clock and the first sampling clock have a same frequency but different phases, and adjusts the second sample value to generate a reference sample value. The calibration circuit applies calibration to the main ADC according to the first sample value and the reference sample value.