Reference Buffer Integrating ADC Capacitor for Noise Reduction
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Solution Overview
Problem
Existing reference buffer technologies face challenges in maintaining accurate reference voltage for analog-to-digital converters (ADCs) due to power consumption variability and increased cost and size from using external capacitors, which are prone to inaccuracies under piezoelectric stresses.
Innovation Solution
A reference buffer topology with an integrator, internal capacitor, and separate gain stages, incorporating a low-pass feedback loop to reduce low-frequency noise and quiescent current, allowing for a single integrated circuit solution with minimal external components, reducing pin count and improving performance in industrial scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external capacitors are used in reference buffer, then reference voltage accuracy is improved, but cost and circuit size increase
Solution Approach 1:
The patent combines the capacitor function directly into the reference buffer circuit by using the ADC's existing capacitor as the reference buffer capacitor, eliminating the need for separate external capacitors. This integration reduces circuit size and component count while maintaining reference voltage accuracy through the buffer's internal architecture.
Solution Approach 2:
The reference buffer is designed to serve multiple functions: it provides reference voltage buffering, filters noise through its internal capacitor, and interfaces with the ADC using the ADC's own capacitor. This multi-functionality eliminates the need for dedicated external capacitors, reducing overall circuit size while maintaining accuracy.
2Measurement precision
If external capacitors are used in reference buffer, then reference voltage accuracy is improved, but cost increases
Solution Approach 1:
The patent merges the reference buffer capacitor function with the ADC's internal capacitor, eliminating the need for separate external capacitor components. This reduction in component count directly lowers manufacturing cost while maintaining reference voltage accuracy through the buffer's internal design.
Solution Approach 2:
The reference buffer design allows the ADC's own capacitor to serve dual purposes: as the ADC's internal capacitor and as the reference buffer's capacitor. This self-service approach eliminates the need for additional external capacitors, reducing both cost and component count while maintaining performance.
3Stability of the object's composition
If reference buffer is added to maintain reference voltage accuracy, then reference voltage stability is improved, but device complexity increases
Solution Approach 1:
The patent combines the reference buffer functionality with the ADC's existing capacitor and internal architecture, eliminating the need for separate external components. This integration maintains reference voltage stability through the buffer's internal design while reducing overall circuit complexity by removing external components and simplifying the bill of materials.
4Measurement precision
If integrator and gain stages are integrated into reference buffer, then reference voltage accuracy is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent integrates the integrator and gain stages within the reference buffer using the ADC's existing capacitor and internal architecture. By consolidating these functions into a single integrated circuit block, the patent reduces the number of discrete components and interconnections, thereby reducing cumulative manufacturing tolerances and improving overall manufacturing precision despite the enhanced functionality.
Data Source
AI summary
A system includes: a reference buffer coupled to an input supply voltage; an analog-to-digital converter (ADC) coupled to an output of the reference buffer; and an output capacitor coupled between the output of the reference buffer and a ground node. The reference buffer includes: an integrator; an internal capacitor coupled between an output of the integrator and the ground node; a first gain stage with an input coupled to the output of the reference buffer; and a second gain stage with an input coupled to the output of the integrator. The output of the first gain stage is combined with the output of the integrator using a combine circuit.


