Reference Voltage Buffer Topology for Fast Settling Under PVT Variation
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Solution Overview
Problem
Analog-to-digital converters face challenges with reference voltage buffers experiencing settling issues, signal instability due to process-voltage-temperature (PVT) variations, and the need for faster settling times and larger full-scale designs, which can lead to unstable reference voltages.
Innovation Solution
A reference voltage buffer design incorporating a reference voltage generator, operational amplifiers, transistors, and resistive loads with active devices, where the loads and reference voltage generator have matching characteristics to address PVT variations and utilize an open-loop design for enhanced noise tolerance and settling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the reference voltage buffer uses active devices as loads to generate reference voltages, then the full-scale can be designed larger, but the reference voltage becomes unstable due to PVT variations
Solution Approach 1:
The patent creates a copy of the reference voltage buffer circuit with matched components (second buffer circuit with transistors M11-M14 and resistors R11-R14 matching the first buffer circuit). This copy is used to generate a compensated reference voltage that is immune to PVT variations, thereby maintaining stability while allowing the original buffer to operate with large full-scale using active devices.
Solution Approach 2:
The patent changes the parameters of the reference voltage generation by using two different configurations: the first buffer circuit (with active devices for large full-scale) and the second buffer circuit (with matched components for PVT compensation). By combining these two different parameter sets, the system achieves both large full-scale and PVT insensitivity.
2Loss of time
If the settling time of the reference voltage buffer is designed shorter to match faster clock frequencies, then the reference voltage stability improves during sampling, but the buffer requires more aggressive design that may compromise full-scale range
Solution Approach 1:
The patent segments the reference voltage buffer into two independent but related circuits: the first buffer circuit (M1-M4, R1-R4) optimized for fast settling with active device loads, and the second buffer circuit (M11-M14, R11-R14) optimized for PVT compensation. This segmentation allows each circuit to be optimized for its specific function without compromising the other.
3Object-affected harmful factors
If the reference voltage buffer is designed with large full-scale to improve noise tolerance, then the signal quality improves, but the reference voltages become unstable
Solution Approach 1:
The patent introduces an intermediary mechanism - the second buffer circuit with matched components that generates a PVT-compensated reference voltage. This intermediary circuit acts as a mediator that provides stability to the overall reference voltage system, allowing the first buffer circuit to operate with large full-scale for improved noise tolerance without sacrificing stability.
Data Source
AI summary
The present invention provides a reference voltage buffer comprises a reference voltage generator, a first operational amplifier, a first transistor, a first group of resistors, a first load, a second transistor, a second group of resistors and a second load. In the reference voltage buffer, the first load and the second load use active device to increase the settling time, and the first load, the second load and the reference voltage generator of the reference voltage buffer are resigned to have the same characteristics in response to the temperature variation to overcome the PVT issue, and the first load and the second load of the reference voltage buffer use the open-loop design to have large full-scale of the output reference voltages.