Reference Buffer Circuit Stabilizing Transconductance Against PVT Variations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing reference buffer circuits in integrated circuits are sensitive to process, voltage, and temperature (PVT) variations, as well as load current variations, which affects their overall transconductance and ability to provide the necessary driving capability for subsequent circuits like ADC or DAC.
Innovation Solution
The proposed solution involves a reference buffer design that includes a configuration of transistors forming current mirrors and active loads, with specific device size ratios and bias currents to enhance transconductance, making it insensitive to PVT and load current variations. This design includes multiple stages of amplifiers and a Gm stage, where the transconductance is determined by the device ratios and bias currents, reducing sensitivity to variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple low-gain wide-band amplifiers are used to increase overall transconductance, then the driving capability is improved, but the transconductance becomes sensitive to PVT and load current variations
Solution Approach 1:
The patent implements feedback mechanisms where the output of later amplifier stages is fed back to earlier stages. Specifically, the output of the third amplifier is fed back to the second amplifier, and further feedback is provided to the first amplifier. This feedback structure stabilizes the overall transconductance against PVT and load current variations while maintaining high driving capability through the cascaded amplifier configuration.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting bias currents and transistor sizing ratios to compensate for PVT variations. The bias circuitry is designed to maintain optimal operating points across process, voltage, and temperature ranges, thereby stabilizing the transconductance parameter despite environmental changes and load variations.
2Power
If high gain is required for reference buffer, then the stability becomes a concern
Solution Approach 1:
The patent divides the high-gain reference buffer into multiple separate amplifier stages (first, second, and third amplifiers), each contributing a portion of the total gain. This segmentation allows each individual stage to be stabilized independently through feedback mechanisms, while the cascaded configuration achieves the required overall high gain. The feedback from later stages to earlier stages ensures stability is maintained throughout the signal path.
Data Source
AI summary
Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.