Configurable Reference Cache and On-Chip Buffer for Low-Latency Video Decoding
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Solution Overview
Problem
Conventional video decoding techniques cause delays in displaying image portions due to the dependency on surrounding image portions, leading to reduced quality and increased latency.
Innovation Solution
A video decoder with a configurable reference cache and on-chip memory buffer is used, where the on-chip memory buffer stores reconstructed image portions before adjustment, and the adjusted image portions are stored in a reference cache for subsequent use, with the cache size configured based on video coding information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If reconstructed image portions are adjusted based on surrounding image portions before display, then quality of subsequent reconstructions is maintained, but display latency increases
Solution Approach 1:
The patent divides the on-chip memory into separate regions: a reference cache region for storing adjusted image portions and a buffer region for storing reconstructed image portions. This segmentation allows the system to simultaneously maintain both unadjusted and adjusted reference images, enabling quality reconstruction without forcing sequential adjustment before display.
Solution Approach 2:
The system pre-adjusts image portions at block boundaries before they are needed for subsequent reconstruction, storing these adjusted portions in the reference cache. This preliminary action ensures that when subsequent blocks need reference data, high-quality adjusted images are already available, reducing the need for delay while maintaining quality.
2Manufacturing precision
If adjusted image portions are stored in reference cache for subsequent reconstruction, then quality of subsequent reconstructions is maintained, but memory resources are consumed
Solution Approach 1:
The patent applies different quality levels to different regions of the image. Specifically, block boundary portions are adjusted and stored in the reference cache to ensure high quality for subsequent reconstruction, while non-boundary portions can use unadjusted reconstructed images. This local quality approach maintains necessary quality only where needed, optimizing memory usage.
3Device complexity
If conventional video decoding is used with sequential adjustment, then device complexity is reduced, but productivity decreases due to reconstruction delays
Solution Approach 1:
The patent merges the reference cache and buffer memory into a single on-chip memory structure with distinct regions. This combining approach maintains relatively simple device architecture while enabling parallel operations: reconstructed images are stored in the buffer region and adjusted images are stored in the reference cache region, both within the same on-chip memory, thus improving productivity without significantly increasing complexity.
Data Source
AI summary
A device includes an on-chip memory and one or more processors coupled to the on-chip memory. The one or more processors are configured to configure a reference cache of the on-chip memory to have a reference cache size based on video coding information. The on-chip memory includes an on-chip memory region that is external to the reference cache. The one or more processors are also configured to assign a portion of the on-chip memory region to buffer data associated with operation of a video decoder.