Reference-Cell ADC Window Adjustment for Multi-Level Memory Reads
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Solution Overview
Problem
Traditional solid-state memory devices face inefficiencies in programming and reading operations due to their binary nature, which becomes increasingly troublesome as more bits are stored on each multi-level cell (MLC), leading to longer operation times and lower storage capacities compared to mechanical hard disk drives (HDDs).
Innovation Solution
The memory devices utilize threshold voltage ranges to represent multiple data bits, allowing for single program and read operations that handle complete bit patterns rather than discrete bits, and employ analog-to-digital conversion using sample and hold circuitry to manage these voltage signals, enabling efficient storage and retrieval of data across a continuum of threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If binary operations are used for reading and programming memory cells, then the operation process is simple and reliable, but the operation time increases and storage capacity per cell decreases as more bits are stored
Solution Approach 1:
The patent segments the analog voltage range into multiple threshold voltage ranges, where each range represents a specific bit pattern. Instead of performing multiple binary operations to read each bit sequentially, the system performs a single analog-to-digital conversion that simultaneously determines all bits stored in the multi-level cell by comparing the read voltage against the segmented threshold ranges.
Solution Approach 2:
The patent changes the operational parameter from discrete binary voltage levels to continuous analog voltage levels with multiple threshold ranges. This parameter change enables the memory cell to store multiple bits by representing different bit patterns as distinct voltage levels within specific ranges, allowing parallel retrieval of multiple bits through a single read operation.
2Quantity of substance
If multi-level cells store more bits per cell, then storage capacity increases, but the number of binary operations required increases leading to longer operation times
Solution Approach 1:
The patent performs preliminary action by pre-defining multiple threshold voltage ranges during memory cell programming, where each range corresponds to a specific bit pattern. During read operations, this preliminary segmentation allows the system to directly compare the read voltage against all threshold ranges simultaneously, retrieving multiple bits in a single operation without requiring sequential binary comparisons.
Solution Approach 2:
The patent merges multiple binary read operations into a single analog-to-digital conversion operation. By combining the retrieval of all bits stored in a multi-level cell into one simultaneous operation, the system achieves faster access times while maintaining high storage capacity, as the analog voltage naturally encodes all bit information that can be decoded through threshold comparison.
3Ease of manufacture
If traditional binary operations are used, then the read and programming processes are straightforward, but storage capacity per cell is limited compared to multi-level cells
Solution Approach 1:
The patent replaces the mechanical sequential binary operation system with an electronic analog-to-digital conversion system. Instead of performing multiple discrete binary comparisons through sequential logic operations, the system uses continuous analog voltage measurement and comparison against threshold ranges, enabling simultaneous retrieval of multiple bits and significantly increasing storage capacity per cell while maintaining manufacturing feasibility.
Data Source
AI summary
An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array.