Reference Cell Read Disturb Reduction via Local Drain Voltage Control
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Solution Overview
Problem
Non-volatile memory (NVM) cells, particularly reference cells, experience significant read disturb due to the high drain voltage used during read operations, leading to potential errors and reduced reliability, especially since reference cells undergo many more read cycles than array cells.
Innovation Solution
Applying a lower drain voltage specifically to reference cells compared to array cells, while maintaining the same global bitline voltage, reduces read disturb by using circuitry such as clamping devices or resistors to lower the drain voltage at the reference cell's port, thereby minimizing the impact on the sensing path matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high drain voltage is used during read operations, then read speed and sensing accuracy are improved, but read disturb increases leading to potential errors and reduced reliability
Solution Approach 1:
The patent applies different drain voltages to different cell types: reference cells use a lower first drain voltage to minimize read disturb, while array cells use a higher second drain voltage to ensure accurate sensing. This local differentiation resolves the contradiction by optimizing voltage levels for each cell type's specific requirements.
Solution Approach 2:
The patent segments the memory array into reference cells and array cells, with separate voltage control paths. Reference cells are read with a first drain voltage through first bitlines, while array cells are read with a second drain voltage through second bitlines, allowing independent voltage optimization for each segment.
2Reliability
If different drain voltages are applied to reference cells and array cells, then read disturb is reduced in reference cells, but device complexity increases
Solution Approach 1:
The patent uses a single voltage source that can output multiple voltage levels (first and second drain voltages), and a voltage selector that routes the appropriate voltage to the appropriate cell type. This multi-functional approach reduces complexity compared to having completely separate voltage sources for reference and array cells.
Solution Approach 2:
The patent introduces a voltage selector as an intermediary component that receives a single drain voltage input and selectively outputs either the first or second drain voltage to reference or array cells respectively. This mediator simplifies the overall voltage control architecture by consolidating multiple voltage sources into one.
Data Source
AI summary
A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the same as one another to maintain main path capacitance matching, while drain voltages on local bitlines (LBLs) for the reference cells may be lower than the drain voltage on local bitlines (LBLs) for the array cells to reduce second bit effect. Reducing the drain voltage of the reference cell at its drain port may be performed using a clamping device or a voltage drop device.