Memory Chip Impedance Calibration with Reference-Chip Parallel ZQ Copying
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Solution Overview
Problem
Existing memory systems require extensive time for calibration operations, particularly in calibrating the output impedance of semiconductor storage devices, which can be inefficient and time-consuming, especially when multiple chips need to be calibrated.
Innovation Solution
A semiconductor device architecture that includes a reference chip for ZQ calibration and subsequent chip calibration, where the output impedance of multiple chips is calibrated using a higher driving capability pull-up and pull-down circuit, allowing for parallel calibration operations and reducing the overall calibration time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional sequential calibration method is used for multiple chips, then calibration precision can be maintained, but calibration time becomes excessively long
Solution Approach 1:
The calibration process is segmented into two distinct phases: ZQ calibration performed once on a reference chip to establish precise impedance values, and subsequent chip calibration that quickly replicates these values across other chips. This segmentation allows the time-consuming precise calibration to be performed only once, while other chips receive rapid calibration with comparable precision.
Solution Approach 2:
The reference chip undergoes comprehensive ZQ calibration in advance to establish accurate impedance reference values before other chips are calibrated. This preliminary action creates a foundation that enables faster calibration of subsequent chips while maintaining precision, as they can reference the pre-calibrated values rather than performing full calibration sequences.
2Measurement precision
If ZQ calibration is performed on each chip individually, then accurate impedance calibration is achieved, but the overall calibration process becomes inefficient
Solution Approach 1:
Instead of performing independent ZQ calibration on each chip, the system performs ZQ calibration once on a reference chip and then copies the calibrated impedance values to subsequent chips. This copying approach maintains impedance calibration accuracy across all chips while dramatically improving calibration efficiency by eliminating redundant calibration operations.
Solution Approach 2:
The reference chip serves multiple functions: it undergoes the full ZQ calibration process to establish accurate reference values, and then its calibrated values are used to calibrate all other chips in the system. This multi-functionality allows a single chip to enable efficient calibration of the entire system while maintaining precision.
3Loss of time
If higher driving capability pull-up and pull-down circuits are implemented, then parallel calibration of multiple chips is enabled, but circuit complexity increases
Solution Approach 1:
The pull-up and pull-down circuits are designed with dynamic switching capabilities that allow them to rapidly change states during parallel calibration operations. This dynamic behavior enables multiple chips to be calibrated simultaneously by quickly responding to calibration signals, reducing overall calibration time while managing circuit complexity through intelligent timing and control.
Data Source
AI summary
A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.