Reference Clock Generation Without Crystal Oscillators
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Solution Overview
Problem
Conventional data transceiving systems rely on expensive and space-consuming crystal devices to generate accurate reference clock signals, which are prone to frequency errors and cannot tolerate significant deviations in serial data transmission.
Innovation Solution
A data transceiving system utilizing a voltage controlled oscillator, a phase lock loop (PLL) unit, and a data receiver to generate and adjust a reference clock signal, where the PLL clock signal is compared with the input data stream's clock signal to produce a voltage adjusting signal, allowing the oscillator to lock the clock frequency to the base frequency of the input data stream, thereby eliminating the need for a crystal device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a crystal device is used to generate a reference clock signal, then the frequency accuracy is improved (less than 100 ppm error), but the manufacturing cost increases and the circuit board space occupation increases
Solution Approach 1:
The patent replaces the expensive crystal device with a voltage controlled oscillator (VCO) that is cheaper and can be integrated into the chip. The VCO generates the reference clock signal without requiring a crystal device, thereby reducing manufacturing cost while maintaining acceptable frequency accuracy through feedback control
Solution Approach 2:
The patent implements a feedback mechanism where the data receiver compares the PLL clock signal with the clock signal of the input data stream and generates a voltage adjusting signal. This feedback loop allows the VCO to automatically correct frequency deviations, maintaining frequency accuracy without requiring a crystal device
2Measurement precision
If a crystal device is used to generate a reference clock signal, then the frequency accuracy is improved (less than 100 ppm error), but the circuit board space occupation increases
Solution Approach 1:
The patent replaces the external crystal device with an integrated voltage controlled oscillator (VCO) that can be fabricated directly on the chip. This integration eliminates the need for separate crystal components and their mounting space on the circuit board, thereby reducing overall space occupation
Solution Approach 2:
The patent merges the reference clock generation function into the integrated chip by incorporating the VCO within the data transceiver. This consolidation combines multiple functions (clock generation, data transmission, and reception) into a single integrated unit, reducing the number of external components and circuit board space requirements
3Reliability
If the reference clock frequency accuracy is improved to less than 100 ppm, then the serial data transmission reliability is improved, but the system complexity increases due to requiring a crystal device
Solution Approach 1:
The patent implements a feedback control system where the data receiver compares the PLL clock signal with the incoming data stream clock signal and generates a voltage adjusting signal. This feedback mechanism automatically corrects frequency deviations, ensuring transmission reliability without requiring the added complexity of a crystal device
Solution Approach 2:
The patent enables the system to self-correct frequency deviations through the feedback loop. The voltage controlling signal generated by the data receiver automatically adjusts the VCO frequency to match the incoming data stream, making the system self-regulating and reducing the need for external precision components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the generation of a PLL clock signal with accurate frequency, reducing frequency errors to within acceptable limits without using a crystal device, thus reducing manufacturing costs and circuit board space.
Implementation Method 1
a voltage controlled oscillator, a phase lock loop (PLL) unit
Implementation Method 2
The PLL unit is coupled to the voltage controlled oscillator and used for increasing a clock frequency of the reference clock signal to generate a PLL clock signal
Implementation Method 3
used for comparing the PLL clock signal with the clock signal of an input data stream and accordingly outputting a voltage adjusting signal
Implementation Method 4
The voltage controlled oscillator adjusts the clock frequency of the reference clock signal according to the voltage adjusting signal, so as to lock the clock frequency of the PLL clock signal generated by the PLL unit to a base frequency of the clock signal of the input data stream
Data Source
AI summary
A method and a data transceiving system for generating a reference clock signal are provided. The data transceiving system comprises a voltage controlled oscillator, a phase lock loop (PLL) unit, and a data receiver. The voltage controlled oscillator is used to generate a reference clock signal. The PLL unit is used to increase a clock frequency of the reference clock signal to generate a PLL clock signal. The data receiver is used to compare the PLL clock signal with a clock signal of an input data stream, so as to output a voltage adjusting signal to the voltage controlled oscillator. The voltage controlled oscillator adjusts the clock frequency of the reference clock signal to be generated according to the reference clock signal, so as to lock the clock frequency of the PLL clock signal to a base frequency of the clock signal of the input data stream.