Reference Clock Duty Cycle Calibration for Low Phase Noise
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Solution Overview
Problem
Current communication systems face limitations in data transmission quality and speed due to phase noise from reference clocks, particularly in high-frequency bandwidth and MIMO applications, where reducing reference clock noise is essential to meet stringent EVM requirements.
Innovation Solution
A reference clock duty cycle calibration circuit comprising a low-noise low-dropout regulator, an oscillation circuit, a duty cycle adjustment circuit, and a duty cycle detection circuit, which adjusts the duty cycle of the reference clock signal based on detected deviations from a preset duty cycle, using a low-noise voltage and proportional reference voltage adjustments to minimize noise and improve communication performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional reference clock is used to meet high data transmission speed requirements, then data transmission speed is improved, but phase noise increases which degrades communication performance
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle detection circuit continuously monitors the reference clock signal and feeds back duty cycle deviation information to the duty cycle adjustment circuit. This closed-loop feedback system dynamically corrects duty cycle deviations, reducing phase noise while maintaining high data transmission speeds required for 160 MHz bandwidth and MIMO operations
Solution Approach 2:
The patent changes the duty cycle parameter of the reference clock signal dynamically. By detecting duty cycle deviations and adjusting the duty cycle through the duty cycle adjustment circuit, the system optimizes the clock signal quality to reduce phase noise, thereby improving EVM performance while maintaining high data transmission speeds
2Reliability
If higher radio frequency bandwidth and MIMO are used to improve data transmission quality and speed, then communication performance requirements increase, but phase noise from reference clock becomes the main limiting factor
Solution Approach 1:
The feedback mechanism continuously monitors duty cycle deviations and adjusts the reference clock signal accordingly, ensuring stable clock quality that supports high-order modulation and MIMO operations while maintaining the required -32 dB RMS EVM performance
Solution Approach 2:
The duty cycle calibration circuit performs self-correction by automatically detecting its own duty cycle deviations and adjusting them without external intervention. This self-service capability ensures the reference clock maintains optimal performance for demanding wireless communication applications
3Object-affected harmful factors
If duty cycle calibration is implemented to reduce reference clock noise, then phase noise is reduced, but circuit complexity increases
Solution Approach 1:
The patent merges the duty cycle detection function with the existing reference clock circuitry. The duty cycle detection circuit utilizes the same clock signal paths and integrates closely with the phase-locked loop components, reducing the need for separate independent circuits and thereby minimizing overall system complexity while effectively reducing reference clock noise
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces reference clock noise, enhancing communication performance by dynamically adjusting the duty cycle of the reference clock signal, thereby improving data transmission quality and speed in wireless communication systems.
Implementation Method 1
a first low-noise low-dropout regulator, configured to provide a low-noise voltage
Implementation Method 2
an oscillation circuit, configured to generate a sine wave signal under the driving of the low-noise voltage
Data Source
Figure 1
Figure 2a~2b
Figure 3a
AI summary
The present invention discloses a reference clock duty cycle calibration circuit. The circuit includes a low-noise low-dropout regulator, an oscillation circuit, a duty cycle adjustment circuit, and a duty cycle calibration circuit. A duty cycle detection circuit of the reference clock duty cycle calibration circuit detects a duty cycle of a reference clock signal output by the duty cycle adjustment circuit. When determining that the duty cycle of the reference clock signal deviates from a preset duty cycle, the duty cycle detection circuit adjusts an amplitude of an output signal of the duty cycle detection circuit, and the duty cycle of the reference clock signal output by the duty cycle adjustment circuit is adjusted by an output voltage of a digital-to-analog conversion circuit and an output voltage of the low-noise low-dropout regulator. When the reference clock duty cycle calibration circuit in the present invention is used, noise of the reference clock can be effectively reduced, and communication performance can be improved.