Multi-Power Reference Clock Circuit With Constant Duty Cycle
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Solution Overview
Problem
In power management integrated circuits, maintaining a constant duty cycle for reference clocks across multiple power operating modes is challenging, as existing designs often result in degraded duty cycle in high power mode relative to normal power mode, leading to unwanted PLL reference and fractional spurs in RF chips.
Innovation Solution
A power management apparatus and method that includes a first output power transistor in parallel with a second output power transistor and a switch, with a crystal oscillator capacitively coupled to the common gate of both, allowing the reference clock signal to operate at a higher power level by switching the second transistor into parallel operation, maintaining a stable duty cycle across power modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference clock operates in high power mode to reduce phase noise and improve RF quality, then the phase noise performance is improved, but the duty cycle degrades relative to normal power mode
Solution Approach 1:
The output stage is segmented into multiple parallel transistors (first output power transistor and second output power transistor) that can be independently controlled. By switching the second transistor into parallel operation during high power mode, the circuit maintains the ability to drive the load heavily while preserving duty cycle through coordinated control of multiple segmented devices rather than relying on a single transistor operating in a degraded region.
Solution Approach 2:
The circuit dynamically reconfigures its output stage by switching the second output power transistor into parallel with the first transistor when high power mode is activated. This dynamic adaptation allows the circuit to optimize its operating characteristics for each power mode, maintaining stable duty cycle during high power operation by adjusting the effective output impedance and drive capability through the switching action.
2Device complexity
If the duty cycle is allowed to degrade in high power mode to simplify circuit design, then the device complexity is reduced, but unwanted PLL reference and fractional spurs are generated in RF chips
Solution Approach 1:
Rather than using a single complex transistor with difficult control characteristics, the output stage is divided into two simpler transistors that can be independently controlled. This segmentation allows each transistor to operate in a more favorable region, simplifying the control logic while eliminating the harmful spurs that would result from duty cycle degradation in a single-transistor design.
Solution Approach 2:
The second output power transistor acts as an intermediary element that is switched into parallel with the first transistor during high power mode. This intermediary component provides the additional drive capability needed for high power operation while maintaining proper duty cycle, thereby preventing the generation of harmful PLL references and fractional spurs without requiring complex control circuitry.
Data Source
AI summary
A power management apparatus and method for maintaining a substantially constant duty cycle of a reference clock signal in a multi-power oscillator, includes a first output power transistor in electrical parallel with a series arrangement of a second output power transistor and a switch, and a crystal oscillator capacitively coupled to a common gate of the first and second output power transistors, wherein a level of the reference clock signal power output is a normal power level when the switch is open and the level of the reference clock signal power output is a higher power level when the switch is closed to operate the second output power transistor in parallel with the first output power transistor.