Reference Clock Failure Detection for Stable PLL Output
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Solution Overview
Problem
Existing clock signal generation systems face challenges with long-term stability and accuracy due to crystal aging, leading to potential catastrophic system failures from loss of reference clock signals or frequency changes, which are difficult to diagnose and recover from.
Innovation Solution
A method and product that utilize a phase-locked loop to generate an output clock signal based on a selected reference clock signal, which includes monitoring for both gross and quality failures using multiple clock signals, allowing for swift detection and response to errors, such as switching to a backup signal or entering holdover mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single reference clock signal is used for frequency synthesis, then device complexity is reduced, but reliability deteriorates due to potential catastrophic system failure from loss of reference clock signal or frequency changes
Solution Approach 1:
The system performs preliminary monitoring of the reference clock signal for both gross failures (loss of signal, out-of-frequency conditions) and quality failures (frequency drift, jitter, phase errors) before catastrophic system failure occurs. This early detection enables proactive switching to backup references or corrective actions, maintaining reliability without requiring complex redundant systems.
Solution Approach 2:
The system continuously monitors the reference clock signal quality and provides feedback to detect both gross and quality failures. This feedback mechanism enables real-time detection of frequency drift, jitter, and phase errors, allowing the system to respond appropriately by switching references or adjusting operation to maintain reliability.
2Ease of manufacture
If crystal oscillators are used for reference clock generation, then manufacturing cost is reduced, but reliability deteriorates due to long-term instability from crystal aging
Solution Approach 1:
The system performs preliminary monitoring of the crystal oscillator output for signs of aging and frequency drift before complete failure occurs. By detecting quality failures early in the degradation process, the system can switch to backup references or adjust operation, extending the reliable service life of the crystal oscillator while maintaining frequency stability.
Solution Approach 2:
The continuous monitoring system provides feedback on crystal oscillator performance, detecting frequency drift and quality degradation caused by aging. This feedback enables proactive management of the crystal oscillator's lifecycle, maintaining frequency stability despite long-term aging effects.
3Reliability
If monitoring for both gross and quality failures is implemented, then reliability is improved, but device complexity increases due to additional monitoring circuits
Solution Approach 1:
The monitoring system is designed to perform multiple functions using integrated circuits that can detect both gross failures (loss of signal, out-of-frequency) and quality failures (frequency drift, jitter, phase errors) within the clock signal path. This multi-functional approach improves reliability without proportionally increasing device complexity, as the same monitoring infrastructure serves multiple detection purposes.
Data Source
AI summary
A method for generating a clock signal includes selecting a primary reference clock signal or a secondary reference clock signal as a reference clock signal for a phase-locked loop configured to generate an output clock signal. The method includes generating an indication of whether a failure of the reference clock signal has occurred by monitoring the secondary reference clock signal and a plurality of additional clock signals using the reference clock signal. The failure is determined based on whether a gross failure of the reference clock signal has occurred and if the gross failure has not occurred, further based on whether a quality failure of the reference clock signal has occurred.