Reference Clock Gating Circuit for Stable SoC Startup Clocks
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Solution Overview
Problem
System on a chip (SoC) devices face instability issues when generating operating clocks from unreliable external reference clocks, particularly during early power-on stages or transitions from low-power modes, leading to potential abnormal operation and damage.
Innovation Solution
An operating clock generator and reference clock gating circuit that includes a detection circuit with counters and a decision circuit to assess the reliability of an external clock by comparing its frequency to a stable slow clock from a crystal oscillator, generating a gating signal to either allow or reject the external clock as a reference clock based on predetermined conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SoC uses an external reference clock to generate the operating clock, then the operating clock can be generated, but the reference clock may be unstable during early power-on or low-power mode transitions, causing abnormal operation or damage
Solution Approach 1:
The patent applies preliminary action by performing clock stability detection before the operating clock generator uses the external reference clock. The detection circuit checks the frequency stability of the external clock signal in advance, and only when the clock is confirmed stable does the gating component allow it to pass through as the reference clock. This prevents unstable clocks from causing abnormal operation or damage to the SoC.
Solution Approach 2:
The patent introduces an intermediary detection circuit and gating component between the external clock source and the operating clock generator. This intermediary structure monitors the external clock signal's stability and controls whether it reaches the phase-locked loop, thereby protecting the system without requiring direct modification of the external clock source or the generator itself.
2Reliability
If the SoC waits for the external reference clock to become stable before using it, then the reference clock reliability improves, but the system experiences delays during power-on or mode transitions
Solution Approach 1:
The patent applies self-service by enabling the detection circuit to automatically monitor and evaluate the external clock signal's stability without requiring external intervention or manual waiting. The circuit continuously checks the clock frequency against predetermined conditions and autonomously determines when the clock is ready for use, eliminating unnecessary delays while ensuring reliability.
3Reliability
If the SoC implements clock stability detection and gating, then the reference clock reliability improves, but the circuit complexity increases
Solution Approach 1:
The patent extracts the clock detection and gating functionality into a separate, dedicated circuit module that operates independently from the main operating clock generator. This separation allows the detection circuit to be optimized specifically for stability monitoring without adding complexity to the entire clock generation system, making the added complexity more manageable and modular.
Data Source
AI summary
Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.