Reference Clock Frequency Switching for Low-Power RF Synthesis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Mobile communications devices face challenges in reducing power consumption and extending standby and operation time due to limited power supply, particularly in generating frequency signals efficiently.
Innovation Solution
A frequency-generating circuit comprising a frequency synthesizer circuit and a reference clock signal processor that dynamically adjusts the frequency of the reference clock signal based on the required reference clock frequency, using a reference clock controller to generate an indication signal and control signal for the frequency synthesizer circuit, allowing for efficient power management by adjusting the frequency of the radio-frequency clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the frequency of the reference clock signal is increased to meet high reference clock frequency requirements, then the communication performance is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic frequency adjustment of the reference clock signal by the reference clock signal processor based on real-time communication requirements. The frequency can be switched between different levels (e.g., first frequency for high performance, second frequency for power saving) according to the established radio link conditions, making the system adaptable to varying operational demands rather than operating at a fixed high frequency continuously
Solution Approach 2:
The patent changes the frequency parameter of the reference clock signal dynamically. The reference clock signal processor adjusts the frequency parameter based on communication requirements, switching between a first frequency when high performance is needed and a second frequency when power consumption needs to be reduced, thereby optimizing the trade-off between communication performance and power consumption
2Use of energy by moving object
If the frequency of the reference clock signal is decreased to reduce power consumption, then the power usage is optimized, but the communication performance deteriorates
Solution Approach 1:
The system dynamically adjusts the reference clock frequency based on actual communication needs rather than operating at a fixed low frequency. When communication performance requirements increase, the frequency can be raised to ensure reliable operation, while during periods of lower demand, the frequency is reduced to save power, achieving optimal balance throughout the operational cycle
Solution Approach 2:
The frequency parameter is changed adaptively based on communication conditions. The reference clock signal processor monitors communication requirements and adjusts the frequency parameter accordingly, increasing it when performance is needed and decreasing it when power saving is prioritized, ensuring the system maintains adequate performance while optimizing power consumption
3Reliability
If a fixed high frequency is used for the reference clock signal, then the communication performance is maintained, but the power consumption increases continuously
Solution Approach 1:
The patent transitions from a static fixed-frequency approach to a dynamic frequency adjustment mechanism. The reference clock signal processor continuously adapts the reference clock frequency based on radio link conditions and communication requirements, switching between high and low frequency states as needed, thereby eliminating the continuous high power consumption associated with fixed high-frequency operation
Solution Approach 2:
The system employs periodic assessment of communication requirements and adjusts the reference clock frequency accordingly. Rather than maintaining a constant high frequency, the system periodically evaluates whether high performance is needed and switches frequency levels based on these assessments, creating a rhythm of high and low power states that reduces overall energy consumption while maintaining performance when required
Data Source
AI summary
A frequency-generating circuit includes a frequency synthesizer circuit and a reference clock signal processor. The frequency synthesizer circuit receives a processed reference clock signal and generates a radio-frequency clock signal according to the processed reference clock signal. The reference clock signal processor receives an original reference clock signal from an oscillator and processes the original reference clock signal according to an indication signal to generate the processed reference clock signal. The indication signal is generated according to a required reference clock frequency of a communications apparatus. When the required reference clock frequency is high, a frequency of the processed reference clock signal is a multiple of a frequency of the original reference clock signal, and when the required reference clock frequency is low, the frequency of the original reference clock signal is a multiple of the frequency of the processed reference clock signal.