Reference Clock Correction Using Low-Frequency Signal Mixing
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Solution Overview
Problem
Existing clock signal compensation methods, such as phase-locked loops (PLLs), are power inefficient and ineffective for systems with low-frequency source clock oscillators due to low quality factor (Q-factor) LC-tank oscillators, especially in integrated technologies, and are not applicable for oscillators with high motional impedance or wide frequency shifts.
Innovation Solution
A system that generates and controls a low-frequency compensation signal using a compensation module and a mixer to correct the oscillator clock signal, eliminating the need for PLLs by using passive or active mixers and digitally-controlled variable-gain amplifiers, and employing soft-switching techniques to reduce quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase-locked loops (PLLs) are used for frequency compensation, then frequency correction can be achieved, but power consumption increases and phase noise performance deteriorates
Solution Approach 1:
The patent extracts and eliminates the PLL component from the frequency compensation system. Instead of using a PLL to generate and lock a VCO frequency to the reference clock, the invention directly mixes the reference clock signal with a digitally-controlled low-frequency compensation signal to produce the corrected output clock signal. This removal of the PLL eliminates the power-hungry GHz range signal generation while maintaining frequency correction capability.
Solution Approach 2:
The patent introduces a low-frequency compensation signal as an intermediary element. This compensation signal, generated at a frequency much lower than the reference clock (e.g., kHz or low MHz range), serves as the mediator that when mixed with the reference clock produces the frequency-corrected output. This intermediary approach avoids the need for high-frequency VCO operation while achieving the same frequency correction effect.
2Measurement precision
If PLLs with LC-tank VCOs are used, then frequency correction is possible, but phase noise increases due to low Q-factor
Solution Approach 1:
The patent removes the LC-tank VCO from the system architecture. By eliminating the VCO and PLL, the source of phase noise associated with low Q-factor integrated LC tanks is completely removed. The frequency correction is achieved directly through mixing operations on the high-Q reference clock signal without generating noisy intermediate high-frequency signals.
Solution Approach 2:
The patent creates a frequency-corrected copy of the reference clock signal through mixing operations. Instead of generating a new signal from a noisy VCO and locking it to the reference, the invention directly modifies the reference clock by mixing it with a low-frequency compensation signal, producing a clean output that is a frequency-corrected version of the original high-Q reference signal.
3Measurement precision
If electrical feedback-loop loading is used for frequency compensation, then temperature-dependent frequency shifts can be corrected, but the approach becomes intractable for wide frequency shifts (100 ppm or more)
Solution Approach 1:
The patent changes the fundamental parameter being controlled from electrical loading (which has limited effect on high-impedance resonators) to direct frequency mixing. By using a digitally-controlled low-frequency compensation signal that can be programmed to provide any required frequency offset, the system can handle wide frequency shifts (100 ppm or more) regardless of the resonator's motional impedance, making the compensation range adaptable to various oscillator types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate frequency correction of clock signals at lower power consumption and noise levels, utilizing high Q-factor source clock oscillators without generating power-hungry GHz range signals, thereby improving power efficiency and reducing phase noise.
Implementation Method 1
The compensation signal is then mixed with the oscillator clock signal to produce a corrected frequency of the reference clock signal
Data Source
AI summary
A system for reference clock frequency correction is described. The system comprises a compensation module configured to (i) receive, as input, an oscillator signal and one or more control signals, (ii) generate a compensation signal based on the oscillator signal and the one or more control signals, wherein the generated compensation signal is a discretized sinusoidal signal having a controllable frequency, and (iii) output the generated compensation signal. The system further comprises a mixer block configured to (i) receive, as input, the generated compensation signal and the oscillator signal, and (ii) generate an output clock signal by mixing the generated compensation signal with the oscillator signal. A soft-switching method to reduce the effect of quantization noise is further described.