Reference Current Generation Circuit for DRAM Read Reliability
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Solution Overview
Problem
In dynamic random access memory (DRAM) cells with electrically floating body transistors, variations in memory cell characteristics and mismatch in transistor circuitry lead to reduced read window margins, increasing the likelihood of read operation failures, especially in deep sub-micron technologies.
Innovation Solution
A reference current generation circuit that includes a plurality of reference networks, where each network consists of a current driver and a reference cell network with transistors programmed to specific data states, generates a reference current to adjust and control the read operation, thereby improving the accuracy of data sensing by modifying the reference current levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reading is performed with fixed reference current levels, then the read operation is simple to implement, but variations in memory cell characteristics and transistor mismatches reduce read window margins and increase read failures
Solution Approach 1:
The reference current generation circuit dynamically adjusts reference current levels based on sensed memory cell current characteristics. The circuit transitions from fixed reference current to variable reference current that adapts to process variations, thereby maintaining optimal read window margins across different operating conditions and reducing read failures
Solution Approach 2:
The circuit employs feedback mechanisms where the sense amplifier monitors memory cell read currents and uses this information to adjust reference current levels. This closed-loop approach ensures that reference currents remain matched to actual memory cell characteristics despite manufacturing variations, improving read reliability without requiring complex open-loop compensation circuits
2Productivity
If deep sub-micron transistors are used to improve scaling and performance, then device density and speed increase, but leakage current increases and read window margins decrease
Solution Approach 1:
The invention changes the parameter of reference current levels from fixed to variable, allowing the circuit to compensate for the increased leakage current inherent in deep sub-micron transistors. By adjusting reference current magnitudes based on actual cell behavior, the system maintains reliable read windows despite using smaller, faster transistors with higher leakage
3Measurement precision
If multiple reference current levels are generated to compensate for variations, then read accuracy improves, but the reference current generation circuit becomes more complex
Solution Approach 1:
The reference current generation circuit is segmented into multiple independent reference current sources, each optimized for specific current ranges. This modular approach allows the circuit to select appropriate reference levels without requiring a single complex adjustable circuit, thereby improving measurement precision while controlling overall circuit complexity through functional decomposition
Data Source
Figure 1A
Figure 1B~1C
Figure 2A~2B
AI summary
There are many inventions disclosed herein. In one aspect, the present inventions are directed to methods and circuitry to control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference current which is employed by sensing circuitry to sense the data state of a memory cell during a read operation of one or more memory cells. The control, adjustment, determination and/or modification of the reference current levels may be implemented using many different, distinct and/or diverse techniques and circuitry, including both analog and digital techniques and circuitry.