Reference Current Circuit Using Paired MOS for Temperature Stability
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Solution Overview
Problem
Existing reference current circuits struggle to supply a stable and precise reference current across varying ambient temperatures, while also requiring a significant layout area.
Innovation Solution
A reference current circuit is designed using a current mirror circuit, paired MOS transistors with different Fermi levels, and a voltage dividing circuit to generate a stable reference current, while minimizing layout area by allowing short channel lengths for the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If conventional reference current circuits are used to ensure stability across temperature changes, then temperature stability is improved, but layout area increases
Solution Approach 1:
The patent changes the operating parameters of MOS transistors by applying specific gate voltages that exploit the temperature-dependent characteristics of mobility and threshold voltage. By operating depletion mode transistors in a specific region where temperature effects on mobility are compensated by threshold voltage changes, the circuit achieves temperature stability without requiring large layout areas.
Solution Approach 2:
The patent combines enhancement mode and depletion mode MOS transistors in a composite configuration. This composite structure leverages the complementary temperature characteristics of the two transistor types to achieve overall temperature stability while maintaining a compact layout.
2Manufacturing precision
If highly precise resistive elements are used to convert reference voltage to current, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent replaces the mechanical/resistive approach (using highly precise resistive elements for voltage-to-current conversion) with an electronic approach using MOS transistor characteristics. By utilizing the voltage-dependent current characteristics of MOS transistors, the circuit achieves high precision without requiring complex resistive networks.
Solution Approach 2:
The patent changes from using resistive parameters to using transistor electrical parameters (gate voltage, channel conductivity) to achieve the voltage-to-current conversion. This parameter change enables high precision reference current generation through electrical control rather than physical resistance matching.
3Stability of the object's composition
If transistor channel lengths are increased to improve temperature compensation, then temperature stability is improved, but layout area increases
Solution Approach 1:
The patent changes the approach from using geometric parameters (long channel lengths) to using electrical parameters (gate voltage control) to achieve temperature stability. By adjusting the gate voltage to operate in a specific region of the transistor characteristics, temperature compensation is achieved without increasing channel length.
Solution Approach 2:
The patent introduces dynamic control through voltage adjustment to compensate for temperature effects. Rather than relying on fixed geometric dimensions, the circuit uses adjustable voltage parameters to dynamically compensate for temperature-induced changes in transistor characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit achieves high precision and stability in supplying the reference current regardless of ambient temperature changes, while reducing the layout area required, thus addressing both performance and space constraints.
Implementation Method 1
an enhancement mode MOS transistor and a first depletion mode MOS transistor that are paired with each other and that generate a reference voltage based on a difference between a voltage of a source terminal of the enhancement mode MOS transistor and a voltage of a source terminal of the first depletion mode MOS transistor, the enhancement mode MOS transistor being the same as the first depletion mode MOS transistor in conductivity type and impurity concentration of a channel, and being different from the first depletion mode MOS transistor in Fermi level of a gate electrode
Implementation Method 2
a voltage dividing circuit connected to the source terminal of the first depletion mode MOS transistor and configured to supply a divided voltage of the reference voltage
Implementation Method 3
a second depletion mode MOS transistor configured to supply, as the input current, a current based on the divided voltage to the current mirror circuit, the voltage dividing circuit being configured to supply a gate terminal of the second depletion mode MOS transistor with the divided voltage within a voltage range higher than a threshold voltage of the second depletion mode MOS transistor and lower than a cross point at which gate voltage-drain current characteristics of the second depletion mode MOS transistor are independent of temperature
Data Source
AI summary
A reference current circuit includes: a current mirror circuit for supplying Iout based on Iin; an E-mode MOS including a drain that supplies Iout, a gate connected to the drain, and a grounded source; a first D-mode MOS including a gate terminal connected to the gate terminal of the E-mode MOS, and generating Vref; a voltage dividing circuit for supplying a divided voltage (Vdiv) of Vref; and a second D-mode MOS for supplying Iin based on Vdiv. The E-mode MOS is the same as the first D-mode MOS in conductivity type and impurity concentration of a channel, and is different from the first D-mode MOS in Fermi level of a gate electrode. The voltage dividing circuit supplies Vdiv higher than a threshold voltage of the second D-mode MOS and lower than a cross point (X) to a gate terminal of the second D-mode MOS.