Reference Fail Bit Verification Circuit for Non-Volatile Memory Erase Optimization
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Solution Overview
Problem
Conventional reference fail bit verification circuits in non-volatile semiconductor memory devices face challenges in setting an appropriate reference fail number, leading to prolonged erase operations and potential over-erasure of memory cells, as they do not differentiate between erase operation modes.
Innovation Solution
A reference fail bit verification circuit that generates distinct counting signals for different erase modes, allowing for the setting of different reference fail numbers for each mode, thereby controlling the erase voltage effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single reference fail number is used for all erase modes, then the circuit design is simple, but the erase operation time is prolonged and over-erasure occurs
Solution Approach 1:
The reference fail number storage is segmented into multiple storage units, each storing a different reference fail number for different erase modes. The fail bit counter is also segmented to generate multiple counting signals corresponding to different reference fail numbers. This segmentation allows the circuit to use mode-specific reference values without significantly increasing overall circuit complexity.
Solution Approach 2:
The reference fail number is made dynamic by selecting different stored values based on the current erase mode. The circuit dynamically switches between different reference fail numbers (first reference fail number for first mode, second reference fail number for second mode) according to the operational mode signal, allowing optimization for each mode without fixed single-value limitation.
2Productivity
If a high reference fail number is set, then the erase cycle time is short, but the erase distribution becomes worse with many un-erased cells
Solution Approach 1:
Different reference fail numbers are assigned to different erase modes based on their specific requirements. The first erase mode uses a first reference fail number optimized for speed, while the second erase mode uses a second reference fail number optimized for quality. This local quality approach allows each mode to have tailored parameters for its specific operational characteristics.
3Manufacturing precision
If a low reference fail number is set, then the erase distribution is improved, but some memory cells are over-erased increasing post-program time
Solution Approach 1:
The circuit applies different reference fail number thresholds locally to different erase modes. The second erase mode uses a lower second reference fail number to ensure high erase distribution quality and prevent over-erasure, while the first mode uses a higher first reference fail number for faster operation. This resolves the contradiction by allowing mode-specific optimization.
4Ease of operation
If the reference fail number is set without considering erase mode, then the circuit is simple to operate, but the overall erase operation time increases
Solution Approach 1:
The circuit automatically selects the appropriate reference fail number based on the current erase mode without requiring external intervention or complex configuration. The mode selection signal automatically triggers the corresponding reference fail number and counting signal, making the system self-adapting and maintaining ease of operation while optimizing performance for each mode.
Data Source
AI summary
A reference fail bit verification circuit includes a fail bit counter which counts a number of fail bits to generate a first counting signal and a second counting signal, the first counting signal and the second counting signal being activated in response to the number of fail bits counted. The circuit also includes a bit verification block which generates a reference bit verification signal that is activated in response to a transition of the first counting signal and the second counting signal, wherein the reference bit verification signal is activated in response to at least one of the activation of the first counting signal in a first mode, and the activation of the second counting signal in a second mode.