Power Transistor Bias Control with Reference FET Drift Compensation

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Solution Overview

Problem

Power amplifiers in wireless transmission systems face efficiency and linearity issues due to variations in transistor threshold voltages over time, caused by manufacturing, temperature, and aging, leading to inconsistent biasing and reduced performance.

Innovation Solution

A bias control circuit that dynamically determines suitable biasing voltages for power transistors by monitoring a reference transistor integrated into the same semiconductor die, using a charge pump and voltage sensing circuit to adjust for temperature and age-related changes in threshold voltages, ensuring consistent operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a fixed bias voltage is applied to the power transistor, then the initial operation is correct, but the bias accuracy deteriorates over time due to threshold voltage variations

Engineering Contradiction:
Improvebias voltage accuracyVSAvoidoperation consistency over time
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the bias control circuit continuously monitors the power transistor's threshold voltage and dynamically adjusts the bias voltage to maintain accurate operation. This closed-loop approach compensates for threshold voltage drift over time, preventing bias accuracy deterioration while ensuring consistent operational reliability.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent transitions from a static fixed bias voltage approach to a dynamic bias control system that adapts to changing transistor characteristics. The bias control circuit modifies the bias voltage in real-time based on threshold voltage variations, enabling the system to maintain optimal performance despite temporal changes in transistor parameters.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If manual calibration routines are performed to account for transistor variations, then bias accuracy is improved, but the complexity and time required for setup increases

Engineering Contradiction:
Improvebias voltage accuracyVSAvoidcalibration procedure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent enables the bias control circuit to automatically perform calibration functions without requiring manual intervention. The circuit self-adjusts the bias voltage based on real-time threshold voltage measurements, eliminating the need for complex manual calibration routines while maintaining high bias accuracy. This self-service capability reduces both procedural complexity and setup time.

Inventive Principle:
Principle #25Self-service

3Reliability

If the bias voltage is adjusted to compensate for threshold voltage changes, then operational reliability is improved, but the circuit complexity increases

Engineering Contradiction:
Improvebias consistency over timeVSAvoidbias control circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a bias control circuit as an intermediary component between the power transistor and the bias voltage source. This mediator monitors threshold voltage changes and automatically adjusts the bias voltage accordingly, improving operational reliability while containing circuit complexity within a dedicated control module rather than requiring system-wide complexity increases.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4254786A1Bias control circuit for power transistors
Publication Date: 2023.10.04 NXP USA INC
  • EP4254786A1 patent drawingFigure 1
  • EP4254786A1 patent drawingFigure 2
  • EP4254786A1 patent drawingFigure 3

AI summary

A system includes a reference field effect transistor (FET), wherein the reference FET is a depletion mode transistor, and a bias control circuit. The bias control circuit includes a voltage sensor connected to a drain terminal of the reference FET. The voltage sensor is configured to measure a voltage at the drain terminal of the reference FET as a measured voltage, determine a voltage difference between a reference voltage and the measured voltage, and output the voltage difference at a voltage sensor output terminal. The system includes a translation circuit connected the voltage sensor output terminal. The translation circuit is configured to convert the voltage difference into a negative gate bias voltage, and apply the negative gate bias voltage to a gate terminal of the reference FET.