Reference-Free SAR ADC Using Charge Redistribution
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Solution Overview
Problem
Conventional SAR ADCs require a reference voltage that consumes significant power and takes substantial time to settle, limiting their conversion rate and increasing their size and power consumption.
Innovation Solution
A reference-free N-bit SAR ADC is implemented using input sampling switches and (N−1) bit capacitive DAC, where the comparator output couples to binary search logic, and the binary search logic couples to the capacitive DAC, eliminating the need for a reference voltage by using charge redistribution through capacitor switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference voltage is used in conventional SAR ADC, then the ADC can perform binary search comparison, but the reference voltage consumes significant power and takes substantial time to settle
Solution Approach 1:
The patent extracts and eliminates the reference voltage component from the SAR ADC system. Instead of using a separate reference voltage source that consumes power and requires settling time, the invention uses the input voltage itself as the reference by configuring the capacitive DAC to compare against the sampled input voltage, thereby removing the harmful reference voltage element while preserving the binary search comparison function
Solution Approach 2:
The input voltage serves multiple functions simultaneously: it is both the signal to be converted and the reference voltage for comparison. The capacitive DAC is designed to perform both the sampling function and the reference comparison function, eliminating the need for separate reference voltage generation circuitry and reducing overall system complexity
2Measurement precision
If a reference voltage is used in conventional SAR ADC, then the ADC can perform binary search comparison, but it requires substantial time to settle due to time constant RC
Solution Approach 1:
The patent removes the reference voltage source that causes settling time delays. By using the sampled input voltage stored on the sampling capacitor as the comparison reference instead of a separate reference voltage, the system eliminates the RC settling time requirement while maintaining the ability to perform binary search comparisons
Solution Approach 2:
The input voltage is sampled and stored on the sampling capacitor before the binary search process begins. This preliminary sampling action prepares the reference voltage in advance, eliminating the need for settling time during the conversion phase since the reference is already stable and ready for comparison
3Measurement precision
If a reference voltage is used in conventional SAR ADC, then the ADC can perform binary search comparison, but it increases the size and power consumption of the device
Solution Approach 1:
The patent extracts and removes the reference voltage generation circuitry from the SAR ADC system. By configuring the capacitive DAC to use the sampled input voltage as the reference, the invention eliminates separate reference voltage sources, reducing the overall device size and component count while maintaining full binary search comparison functionality
Solution Approach 2:
The capacitive DAC is designed to perform multiple functions: it serves as both the digital-to-analog converter and the reference voltage source for comparison. This multi-functionality reduces the number of separate components needed, thereby decreasing device complexity and size while preserving the binary search comparison capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, achieves a faster conversion rate, simplifies circuitry, and results in a more compact size for the SAR ADC, while maintaining the full scale voltage determination by the combination of sampling and DAC capacitor values.
Implementation Method 1
A capacitive DAC consists of an array of capacitors with binary weighted values. It employs the principle of charge redistribution to generate an analog output voltage during the binary search process.
Implementation Method 2
The charge of pre-charged capacitor is re-distributed to the sampling capacitor which results in a voltage increment on the comparator input.
Data Source
AI summary
A method of eliminating reference voltage of Analog-to-Digital Converter to enhance faster conversion rate, achieve compact size and decrease power consumption for Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).