Reference Frequency Calibration Using PLL Feedback and Divider Tuning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional electronic apparatuses using passive crystals or active oscillators for reference frequency generation incur high costs and circuit area due to the need for external components and limited frequency accuracy, especially in USB communication systems requiring low jitter and high frequency stability.
Innovation Solution
A reference frequency calibration module comprising an oscillator, frequency divider, phase-locked loop, and frequency-offset calibration unit, which generates oscillating signals without external crystals, utilizing a CMOS oscillator to reduce component costs and circuit area, and adjusts the frequency divider parameter based on the phase-locked loop's output to maintain synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If passive crystal or active oscillator is used for reference frequency generation, then frequency accuracy and stability are improved, but circuit area and cost increase due to external components
Solution Approach 1:
The patent extracts and eliminates the external crystal or oscillator component from the system. Instead of using a separate passive crystal or active oscillator, the invention generates the reference frequency directly from the USB clock signal through a frequency synthesis circuit integrated within the device, thereby removing the need for external components and reducing circuit area while maintaining frequency accuracy
Solution Approach 2:
The patent merges the reference frequency generation function with the USB clock signal processing. The frequency synthesis circuit integrates the USB clock input, frequency division, and phase-locked loop functionality into a unified system that generates the reference frequency internally, combining multiple functions into a single integrated circuit block
2Stability of the object's composition
If passive crystal or active oscillator is used for reference frequency generation, then frequency stability is improved, but cost increases due to external components
Solution Approach 1:
The patent removes the expensive external crystal or oscillator component from the bill of materials. By generating the reference frequency internally from the USB clock signal through integrated frequency synthesis, the invention eliminates the need to purchase and assemble external frequency-stabilizing components, thereby reducing manufacturing cost while maintaining frequency stability
Solution Approach 2:
The patent enables the device to generate its own reference frequency using the USB clock signal as input. The frequency synthesis circuit self-regulates to produce a stable reference frequency without requiring external frequency reference components, making the system self-sufficient and eliminating dependency on external components that increase cost
3Measurement precision
If traditional oscillator is used for reference frequency, then frequency accuracy is improved, but device complexity increases
Solution Approach 1:
The patent combines the USB clock signal processing and reference frequency generation into a single integrated frequency synthesis circuit. By merging the USB clock input stage, frequency division, and phase-locked loop into one unified block, the invention reduces device complexity compared to having separate USB interface and separate crystal oscillator circuits
Data Source
AI summary
A reference frequency calibration module is provided. The reference frequency calibration module includes an oscillator, a frequency divider, a phase-locked loop (PLL) and a frequency-offset calibration unit. The frequency divider couples to the oscillator. The phase-locked loop couples to the frequency divider. The frequency-offset calibration unit couples to the frequency divider and the phase-locked loop. The oscillator is configured for operatively generating an oscillating signal having an oscillating frequency. The frequency divider divides the oscillating signal having the oscillating frequency by a first division parameter to generate a first clock signal having a first reference frequency. The phase-locked loop generates a second clock signal having a second reference frequency according to the first clock signal. The frequency-offset calibration unit is configured for operatively generating the first division parameter according to the second clock signal.