Reference-Less Frequency Detector for Multi-Format CDR
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits require a reference clock signal, increasing complexity and cost, and are limited to recovering clock signals from Non-Return to Zero (NRZ) data signals, failing to accommodate other modulation formats.
Innovation Solution
A reference-less CDR circuit that uses sampling circuits and a control circuit to generate control signals for adjusting the frequency of a clock signal based on an input data signal, allowing recovery of clock signals from any modulation format, including NRZ, PAM, and PAM4 data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference clock signal is used in the FLL circuit, then the frequency locking accuracy is improved, but the device complexity and cost increase
Solution Approach 1:
The patent removes the reference clock signal from the FLL circuit, extracting the unnecessary component that causes complexity while maintaining frequency locking capability through alternative means (using the input data signal itself for frequency detection and control)
Solution Approach 2:
The input data signal serves multiple functions: it is both the signal to be recovered and the reference for frequency detection, eliminating the need for a separate reference clock signal and reducing overall system complexity
2Device complexity
If the existing sampling approach using D-type flip flops is used, then the clock signal recovery is simplified, but the adaptability to different modulation formats is reduced
Solution Approach 1:
The frequency detector is designed to handle multiple modulation formats (NRZ, PAM4, and others) through a unified frequency comparison mechanism that does not depend on specific signal characteristics, making the circuit universally applicable while maintaining simplicity
Solution Approach 2:
The patent changes the approach from edge-triggered sampling (which works only for NRZ) to frequency-based comparison that can accommodate different signal formats by adjusting frequency parameters rather than relying on fixed edge transitions
3Device complexity
If the reference-less CDR circuit approach is used, then the system complexity and cost are reduced, but the frequency detection accuracy deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the frequency detector continuously compares the VCO output frequency with the input signal frequency and adjusts the VCO control voltage accordingly, maintaining accurate frequency detection without a reference clock through closed-loop control
Data Source
AI summary
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.