Reference-Less Clock Recovery for Multi-Format Data Signals
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits require a reference clock signal, increasing complexity and cost, and are limited to recovering clock signals from Non-Return to Zero (NRZ) data signals, failing to accommodate other modulation formats.
Innovation Solution
A reference-less CDR circuit that uses sampling circuits and a control circuit to generate control signals for adjusting the frequency of a clock signal based on an input data signal, allowing recovery of clock signals from any modulation format, including NRZ, PAM, and PAM4 data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference clock signal is used in the FLL circuit, then the clock recovery operation can be performed, but the complexity and cost of the circuit increases
Solution Approach 1:
The patent extracts and removes the reference clock signal requirement from the FLL circuit, transforming it into a reference-less architecture. The sampling circuits directly sample the VCO clock signal using transitions from the input data signal itself, eliminating the need for external reference clock components and reducing circuit complexity while maintaining clock recovery functionality
Solution Approach 2:
The input data signal serves a dual purpose: it carries the data information and simultaneously provides the sampling triggers for the sampling circuits. The transitions in the input data signal automatically generate the control signals needed for sampling, making the system self-sufficient without requiring external reference clock signals
2Reliability
If D-type flip flops sample the clock signal at the transition edge of the input data signal, then the clock signal can be recovered, but the input data signal is limited to NRZ format only
Solution Approach 1:
The sampling circuits are designed with universal functionality to handle multiple data signal formats (NRZ, PAM, PAM4, and others). The circuits detect transitions in the input data signal regardless of the specific modulation format and use these transitions to trigger sampling of the VCO clock signal, making the clock recovery mechanism adaptable to various data encoding schemes
Solution Approach 2:
The patent changes the operating parameters of the sampling circuits to accommodate different data signal formats. By adjusting the sampling threshold and trigger detection parameters, the circuits can reliably detect transitions in various modulation formats and accordingly adjust the sampling timing to recover the clock signal effectively for each format
Data Source
AI summary
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.