Reference-Less Clock Recovery for Non-NRZ Data Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock and data recovery (CDR) circuits require a reference clock signal, adding complexity and cost, and are limited to recovering clock signals from Non-Return to Zero (NRZ) data signals, failing to accommodate other data signal formats.
Innovation Solution
A reference-less CDR circuit that uses sampling circuits and a control circuit to generate control signals for adjusting the frequency of a clock signal based on an input data signal, allowing recovery of clock signals from any data signal format, including NRZ, PAM, and PAM4, without the need for a separate reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference clock signal is used in the FLL circuit, then the clock recovery operation can be performed, but the complexity and cost of the circuit increases
Solution Approach 1:
The patent extracts and removes the reference clock signal requirement from the FLL circuit, transforming it into a reference-less configuration. The sampling circuit samples the VCO output clock signal directly using transitions from the input data signal, eliminating the need for external reference clock inputs and associated circuitry.
Solution Approach 2:
The circuit uses its own internally generated clock signal from the VCO as the sampling clock, rather than requiring an external reference. The system serves itself by using the VCO output to sample the data signal transitions, which then control the VCO frequency through the FLL mechanism.
2Reliability
If D-type flip flops are used to sample the clock signal at data signal transitions, then clock recovery can be achieved, but the input data signal is limited to NRZ format only
Solution Approach 1:
The patent replaces the NRZ-specific D-type flip flop with a universal sampling circuit that can detect transitions in any data signal format (NRZ, PAM4, RZ, etc.). The sampling circuit uses a latch-based design that responds to any voltage transition edge, making the clock recovery function adaptable to multiple data encoding schemes without requiring format-specific circuitry.
Solution Approach 2:
The invention changes the operational parameters of the sampling mechanism from being edge-triggered by specific NRZ transitions to being level-sensitive latches that can capture transitions from various signal formats. The sampling circuit monitors voltage transitions regardless of their specific timing or amplitude characteristics, enabling compatibility with different data signal parameters.
Data Source
AI summary
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.