Reference-Less Clock Recovery for PAM and NRZ Data Signals
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits require a reference clock signal, adding complexity and cost, and are limited to recovering clock signals from Non-Return to Zero (NRZ) data signals, failing to accommodate other data signal formats.
Innovation Solution
A reference-less CDR circuit that uses sampling circuits and a control circuit to generate control signals for adjusting the frequency of a clock signal based on an input data signal, allowing recovery of clock signals from any data signal format, including NRZ, PAM, and PAM4, without the need for a separate reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference clock signal is used in the FLL circuit, then the clock recovery accuracy is improved, but the device complexity and cost increase
Solution Approach 1:
The patent removes the reference clock signal from the FLL circuit, extracting the unnecessary component that adds complexity. The circuit achieves clock recovery without requiring an external reference clock, thereby reducing device complexity and cost while maintaining functionality through alternative frequency comparison methods
Solution Approach 2:
The FLL circuit is modified to be self-sufficient by eliminating the external reference clock requirement. The circuit uses its own internal resources and the input data signal to perform frequency comparison and clock recovery, making the system self-service and reducing external dependencies
2Adaptability or versatility
If the existing sampling approach is used with D-type flip flops, then the clock signal can be recovered from NRZ data signals, but the adaptability to other data signal formats is limited
Solution Approach 1:
The patent modifies the sampling circuit to handle multiple data signal formats (NRZ, PAM, PAM4, etc.) universally. The circuit uses a configurable sampling mechanism that can adapt to different signal characteristics, making the FLL circuit multi-functional and compatible with various modulation formats while maintaining reliable operation
Solution Approach 2:
The sampling circuit is made dynamic and configurable rather than fixed. The circuit can adjust its sampling parameters and behavior based on the detected data signal format, enabling it to reliably process different types of signals by changing its operational characteristics to match the input signal properties
Data Source
AI summary
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.