Reference-Less Frequency Detector for High-Jitter Clock Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed data communication systems face challenges in accurately detecting phase and frequency offsets between clock and data signals, leading to instability and incorrect frequency adjustments due to jitter, especially in systems operating at 10 Gbps to 100 Gbps, which affects data recovery and power consumption.
Innovation Solution
A reference-less frequency detector is implemented using three sampling circuits and a NAND gate to sample clock and data signals, with a delayed data signal to prevent false triggering of frequency corrections under jitter conditions, ensuring accurate frequency alignment without a reference clock or lock detector.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional frequency detection methods are used in high-speed data communication systems, then frequency detection can be performed, but false triggering occurs due to jitter causing instability and incorrect frequency adjustments
Solution Approach 1:
The patent introduces a delay element as an intermediary component that delays one of the sampled signals by a specific time period. This delayed signal serves as a reference that is less susceptible to jitter effects, allowing the frequency detector to compare the original sampled signal with the delayed version to determine frequency offsets more accurately without false triggering.
Solution Approach 2:
The patent applies preliminary action by delaying the data signal before sampling to create a reference signal that is already adjusted for the expected jitter effects. This preliminary delay preparation ensures that when the frequency detection occurs, the comparison between sampled signals is more robust against jitter, preventing false triggering before it can occur.
2Device complexity
If reference-less frequency detection is implemented to reduce complexity, then device complexity is reduced, but jitter tolerance is insufficient leading to false frequency corrections
Solution Approach 1:
The patent segments the frequency detection process into multiple independent sampling operations. Instead of a single complex sampling operation, the system performs separate sampling of the clock signal at different phases using the delayed data signal as a reference, thereby simplifying each individual sampling operation while collectively achieving robust jitter tolerance through the segmented approach.
3Measurement precision
If frequency adjustments are made frequently to maintain synchronization, then data recovery accuracy is improved, but power consumption increases due to unnecessary corrections under jitter conditions
Solution Approach 1:
The patent implements a feedback mechanism where the frequency detector continuously monitors the phase and frequency offsets between clock and data signals using the delayed sampled signals. The detection result feeds back to control frequency adjustments only when actual frequency offsets are detected, rather than making continuous adjustments. This feedback-based approach maintains data recovery accuracy while significantly reducing unnecessary frequency corrections and associated power consumption during jitter conditions.
Data Source
AI summary
An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.